From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 May 2021 13:39:46 +0000 (+0100)
Subject: add testloop.s
X-Git-Tag: xlen-bcd~579
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b211615f1b141935818e0e093b77eb6714b35578;p=openpower-isa.git

add testloop.s
---

diff --git a/src/test/basic_pypowersim/.gitignore b/src/test/basic_pypowersim/.gitignore
new file mode 100644
index 00000000..9cd5496e
--- /dev/null
+++ b/src/test/basic_pypowersim/.gitignore
@@ -0,0 +1,3 @@
+*.bin
+*.elf
+*.o
diff --git a/src/test/basic_pypowersim/Makefile b/src/test/basic_pypowersim/Makefile
index f3ddf216..cff37389 100644
--- a/src/test/basic_pypowersim/Makefile
+++ b/src/test/basic_pypowersim/Makefile
@@ -11,7 +11,7 @@ sim: kernel.bin
 clean:
 	rm *.o *.elf *.bin
 
-kernel.elf: test.o
+kernel.elf: testloop.o
 	$(TOOLCHAIN)-ld $^ -EL -o $@ -T memmap
 
 kernel.bin: kernel.elf
diff --git a/src/test/basic_pypowersim/testloop.s b/src/test/basic_pypowersim/testloop.s
new file mode 100644
index 00000000..b0272953
--- /dev/null
+++ b/src/test/basic_pypowersim/testloop.s
@@ -0,0 +1,5 @@
+addi 1, 0, 0
+addi 2, 0, 7
+mtspr 9, 2       /* set ctr to 7 */
+addi 1, 1, 5
+bc 16, 0, -0x4  /* bdnz to the addi above */