From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 30 Aug 2022 07:08:52 +0000 (+0300)
Subject: power_insn: fix representation
X-Git-Tag: sv_maxu_works-initial~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2281365ec8c4470fd78f2fdb3987b76659c01db;p=openpower-isa.git

power_insn: fix representation
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index b06bbbe3..b4ce51c6 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -612,10 +612,9 @@ class PrefixedInstruction(Instruction):
     def disassemble(self, db):
         record = db[self.suffix]
         if record is None:
-            yield f".long 0x{int(self.prefix):08x}"
-            yield f".long 0x{int(self.suffix):08x}"
+            yield f".llong 0x{int(self):016x}"
         else:
-            yield f".llong 0x{int(self):08x} # {record.name}"
+            yield f".llong 0x{int(self):016x} # {record.name}"
 
 
 class SVP64Instruction(PrefixedInstruction):
@@ -651,9 +650,9 @@ class SVP64Instruction(PrefixedInstruction):
     def disassemble(self, db):
         record = db[self.suffix]
         if record is None:
-            yield f".llong 0x{int(self):08x}"
+            yield f".llong 0x{int(self):016x}"
         else:
-            yield f".llong 0x{int(self):08x} # sv.{record.name}"
+            yield f".llong 0x{int(self):016x} # sv.{record.name}"
 
 
 class Database: