From: Michael Nolan Date: Thu, 2 Apr 2020 17:01:46 +0000 (-0400) Subject: Combine a selectable number of rounds into one pipeline stage X-Git-Tag: ls180-24jan2020~96 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b24bde5eba80e8078188b61c22170e80a45cf265;p=ieee754fpu.git Combine a selectable number of rounds into one pipeline stage --- diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py index a477d200..bcdeae9d 100644 --- a/src/ieee754/cordic/pipe_data.py +++ b/src/ieee754/cordic/pipe_data.py @@ -37,8 +37,10 @@ class CordicData: class CordicPipeSpec: - def __init__(self, fracbits): + def __init__(self, fracbits, rounds_per_stage): self.fracbits = fracbits + # Number of cordic operations per pipeline stage + self.rounds_per_stage = rounds_per_stage self.M = (1 << fracbits) self.ZMAX = int(round(self.M * math.pi/2)) zm = Const(-self.ZMAX) diff --git a/src/ieee754/cordic/sin_cos_pipeline.py b/src/ieee754/cordic/sin_cos_pipeline.py index 42dd6fc5..5bc60e48 100644 --- a/src/ieee754/cordic/sin_cos_pipeline.py +++ b/src/ieee754/cordic/sin_cos_pipeline.py @@ -17,17 +17,29 @@ class CordicPipeChain(PipeModBaseChain): class CordicBasePipe(ControlBase): def __init__(self, pspec): ControlBase.__init__(self) + self.pspec = pspec self.cordicstages = [] + initstage = CordicInitialStage(pspec) + stages = [] for i in range(pspec.iterations): - if i == 0: - stages = [CordicInitialStage(pspec), CordicStage(pspec, i)] - else: - stages = [CordicStage(pspec, i)] - stage = CordicPipeChain(pspec, stages) - self.cordicstages.append(stage) + stages.append(CordicStage(pspec, i)) + chunks = self.chunkify(initstage, stages) + print(len(chunks)) + for chunk in chunks: + chain = CordicPipeChain(pspec, chunk) + self.cordicstages.append(chain) self._eqs = self.connect(self.cordicstages) + def chunkify(self, initstage, stages): + chunks = [] + + for i in range(0, len(stages), self.pspec.rounds_per_stage): + chunks.append(stages[i:i + self.pspec.rounds_per_stage]) + chunks[0].insert(0, initstage) + + return chunks + def elaborate(self, platform): m = ControlBase.elaborate(self, platform) for i, stage in enumerate(self.cordicstages): diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py index 809ca7f7..880351ad 100644 --- a/src/ieee754/cordic/test/test_pipe.py +++ b/src/ieee754/cordic/test/test_pipe.py @@ -13,7 +13,7 @@ import random class SinCosTestCase(FHDLTestCase): def run_test(self, inputs, outputs, fracbits=8): m = Module() - pspec = CordicPipeSpec(fracbits=fracbits) + pspec = CordicPipeSpec(fracbits=fracbits, rounds_per_stage=4) m.submodules.dut = dut = CordicBasePipe(pspec) z = Signal(dut.p.data_i.z0.shape())