From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Jun 2020 17:44:13 +0000 (+0100)
Subject: fix imports (allows test command to be run from non-top-level directory)
X-Git-Tag: ls180-24jan2020~54
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b255e143729bb54b9810d3eff7cd8ddb5cd8eaa4;p=ieee754fpu.git

fix imports (allows test command to be run from non-top-level directory)
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 7df7be47..32203884 100755
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -2,11 +2,13 @@
 # SPDX-License-Identifier: LGPL-2.1-or-later
 # See Notices.txt for copyright information
 
-from .core import (DivPipeCoreConfig, DivPipeCoreSetupStage,
-                   DivPipeCoreCalculateStage, DivPipeCoreFinalStage,
-                   DivPipeCoreOperation, DivPipeCoreInputData,
-                   DivPipeCoreInterstageData, DivPipeCoreOutputData)
-from .algorithm import (FixedUDivRemSqrtRSqrt, Fixed, Operation, div_rem,
+from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreConfig,
+                    DivPipeCoreSetupStage,
+                    DivPipeCoreCalculateStage, DivPipeCoreFinalStage,
+                    DivPipeCoreOperation, DivPipeCoreInputData,
+                    DivPipeCoreInterstageData, DivPipeCoreOutputData)
+from ieee754.div_rem_sqrt_rsqrt.algorithm import (FixedUDivRemSqrtRSqrt,
+                        Fixed, Operation, div_rem,
                         fixed_sqrt, fixed_rsqrt)
 import unittest
 from nmigen import Module, Elaboratable, Signal