From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sat, 16 Apr 2022 18:39:41 +0000 (-0500)
Subject: Properly wire core reset to ti_rst
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b25bcf06665b246515186a10b954dcea24df5bf4;p=soc.git

Properly wire core reset to ti_rst

This partially fixes Bug #812
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index a80941db..e41a844c 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -457,13 +457,12 @@ class TestIssuerBase(Elaboratable):
         comb += cd_por.clk.eq(ClockSignal())
 
         # power-on reset delay
-        core_rst = ResetSignal(self.core_domain)
         if self.core_domain != "sync":
             comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
-            comb += core_rst.eq(ti_rst)
+            comb += self.core_rst.eq(ti_rst)
         else:
             with m.If(delay != 0 | dbg.core_rst_o):
-                comb += core_rst.eq(1)
+                comb += self.core_rst.eq(1)
         with m.If(stop_delay != 0):
             # run DMI core-stop as well but on an extra couple of cycles
             comb += dbg.core_stopped_i.eq(1)