From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 30 Sep 2014 09:04:36 +0000 (+0200)
Subject: revert simulation design and add wave
X-Git-Tag: 24jan2021_ls180~2572^2~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b284819d18731d559128ccbfe1c00235da00a557;p=litex.git

revert simulation design and add wave
---

diff --git a/Makefile b/Makefile
index 51f03d58..3afe3935 100644
--- a/Makefile
+++ b/Makefile
@@ -7,7 +7,7 @@ PLATFORM = kc705_impact
 CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -p $(PLATFORM) -t test
 
 csv:
-	cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv -Ot gen_mila_csv True
+	cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv
 	cd $(CURDIR)
 
 bit:
diff --git a/sim/sim.png b/sim/sim.png
new file mode 100644
index 00000000..d4e9e9e7
Binary files /dev/null and b/sim/sim.png differ
diff --git a/sim/wave.do b/sim/wave.do
new file mode 100644
index 00000000..1a0f8ab1
--- /dev/null
+++ b/sim/wave.do
@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_host_source_payload_d
+add wave -noupdate /top_tb/dut/sataphy_host_source_stb
+add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_device_source_payload_d
+add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_device_source_stb
+add wave -noupdate -radix hexadecimal /top_tb/refclk_p
+add wave -noupdate -radix hexadecimal /top_tb/refclk_n
+add wave -noupdate -radix hexadecimal /top_tb/clk200_p
+add wave -noupdate -radix hexadecimal /top_tb/clk200_n
+add wave -noupdate -radix hexadecimal /top_tb/sata_txp
+add wave -noupdate -radix hexadecimal /top_tb/sata_txn
+add wave -noupdate -radix hexadecimal /top_tb/sata_rxp
+add wave -noupdate -radix hexadecimal /top_tb/sata_rxn
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {16623348 ps} 0} {{Cursor 2} {21767465 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 446
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {17730427 ps}
diff --git a/targets/test.py b/targets/test.py
index df2535b6..f617074e 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -88,63 +88,21 @@ class UART2WB(Module):
 
 class TestDesign(UART2WB):
 	default_platform = "kc705"
-	csr_map = {
-		"mila":				10
-	}
-	csr_map.update(UART2WB.csr_map)
 
-	def __init__(self, platform, **kwargs):
+	def __init__(self, platform):
 		clk_freq = 166666*1000
 		UART2WB.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform)
 
-		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, 
-			host=True, default_speed="SATA3")
+		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
 		self.comb += [
 			self.sataphy_host.sink.stb.eq(1),
 			self.sataphy_host.sink.payload.d.eq(0x12345678)
 		]
-
-		import os
-		from miscope import trigger, miio, mila
-		from mibuild.tools import write_to_file
-		from migen.fhdl import verilog
-
-		term = trigger.Term(width=64)
-		self.submodules.mila = mila.MiLa(width=64, depth=2048, ports=[term], with_rle=True)
-
-		gtx = self.sataphy_host.gtx
-		ctrl = self.sataphy_host.ctrl
-
-		mila_dat = (
-			gtx.rxresetdone,
-			gtx.txresetdone,
-
-			gtx.rxuserrdy,
-			gtx.txuserrdy,
-
-			gtx.rxcominitdet,
-			gtx.rxcomwakedet,
-
-			gtx.txcomfinish,
-			gtx.txcominit,
-			gtx.txcomwake,
-
-		)
-
+		self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
 		self.comb += [
-			self.mila.sink.stb.eq(1),
-			self.mila.sink.dat.eq(Cat(*mila_dat))
+			self.sataphy_device.sink.stb.eq(1),
+			self.sataphy_device.sink.payload.d.eq(0x12345678)
 		]
 
-		try:
-			gen_mila_csv = kwargs.pop('gen_mila_csv')
-		except:
-			gen_mila_csv = False
-
-		if gen_mila_csv: 
-			r, ns = verilog.convert(self, return_ns=True)
-			mila_csv = self.mila.get_csv(mila_dat, ns)
-			write_to_file(os.path.join(platform.soc_ext_path, "test", "mila.csv"), mila_csv)
-
 default_subtarget = TestDesign