From: Xionghu Luo Date: Fri, 22 Jan 2021 03:01:24 +0000 (-0600) Subject: rs6000: Support variable insert and Expand vec_insert in expander [PR79251] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b29225597584b697762585e0b707b7cb4b427650;p=gcc.git rs6000: Support variable insert and Expand vec_insert in expander [PR79251] vec_insert accepts 3 arguments, arg0 is input vector, arg1 is the value to be insert, arg2 is the place to insert arg1 to arg0. Current expander generates stxv+stwx+lxv if arg2 is variable instead of constant, which causes serious store hit load performance issue on Power. This patch tries 1) Build VIEW_CONVERT_EXPR for vec_insert (i, v, n) like v[n&3] = i to unify the gimple code, then expander could use vec_set_optab to expand. 2) Expand the IFN VEC_SET to fast instructions: lvsr+insert+lvsl. In this way, "vec_insert (i, v, n)" and "v[n&3] = i" won't be expanded too early in gimple stage if arg2 is variable, avoid generating store hit load instructions. For Power9 V4SI: addi 9,1,-16 rldic 6,6,2,60 stxv 34,-16(1) stwx 5,9,6 lxv 34,-16(1) => rlwinm 6,6,2,28,29 mtvsrwz 0,5 lvsr 1,0,6 lvsl 0,0,6 xxperm 34,34,33 xxinsertw 34,0,12 xxperm 34,34,32 Though instructions increase from 5 to 7, the performance is improved 60% in typical cases. Tested with V2DI, V2DF V4SI, V4SF, V8HI, V16QI on Power9-LE. 2021-01-22 Xionghu Luo gcc/ChangeLog: PR target/79251 PR target/98065 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Ajdust variable index vec_insert from address dereference to ARRAY_REF(VIEW_CONVERT_EXPR) tree expression. * config/rs6000/rs6000-protos.h (rs6000_expand_vector_set_var): New declaration. * config/rs6000/rs6000.c (rs6000_expand_vector_set_var): New function. 2021-01-22 Xionghu Luo gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr79251.p9.c: New test. * gcc.target/powerpc/pr79251-run.c: New test. * gcc.target/powerpc/pr79251.h: New header. --- diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index cdc64bd63c6..4a237ae322a 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1512,9 +1512,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, tree arg1; tree arg2; tree arg1_type; - tree arg1_inner_type; tree decl, stmt; - tree innerptrtype; machine_mode mode; /* No second or third arguments. */ @@ -1566,8 +1564,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, return build_call_expr (call, 3, arg1, arg0, arg2); } - /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */ - arg1_inner_type = TREE_TYPE (arg1_type); + /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0 with + VIEW_CONVERT_EXPR. i.e.: + D.3192 = v1; + _1 = n & 3; + VIEW_CONVERT_EXPR(D.3192)[_1] = i; + v1 = D.3192; + D.3194 = v1; */ if (TYPE_VECTOR_SUBPARTS (arg1_type) == 1) arg2 = build_int_cst (TREE_TYPE (arg2), 0); else @@ -1582,6 +1585,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, TREE_USED (decl) = 1; TREE_TYPE (decl) = arg1_type; TREE_READONLY (decl) = TYPE_READONLY (arg1_type); + TREE_ADDRESSABLE (decl) = 1; if (c_dialect_cxx ()) { stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, @@ -1592,19 +1596,12 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, { DECL_INITIAL (decl) = arg1; stmt = build1 (DECL_EXPR, arg1_type, decl); - TREE_ADDRESSABLE (decl) = 1; SET_EXPR_LOCATION (stmt, loc); stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); } - - innerptrtype = build_pointer_type (arg1_inner_type); - - stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); - stmt = convert (innerptrtype, stmt); - stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); - stmt = build_indirect_ref (loc, stmt, RO_NULL); - stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt, - convert (TREE_TYPE (stmt), arg0)); + stmt = build_array_ref (loc, stmt, arg2); + stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt, + convert (TREE_TYPE (stmt), arg0)); stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); return stmt; } diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 9cca7325d0d..9a46a414743 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -58,6 +58,7 @@ extern bool rs6000_split_128bit_ok_p (rtx []); extern void rs6000_expand_float128_convert (rtx, rtx, bool); extern void rs6000_expand_vector_init (rtx, rtx); extern void rs6000_expand_vector_set (rtx, rtx, rtx); +extern void rs6000_expand_vector_set_var (rtx, rtx, rtx); extern void rs6000_expand_vector_extract (rtx, rtx, rtx); extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx); extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 57bf7f7828e..68832a38952 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6993,6 +6993,12 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx) if (VECTOR_MEM_VSX_P (mode)) { + if (!CONST_INT_P (elt_rtx)) + { + rs6000_expand_vector_set_var (target, val, elt_rtx); + return; + } + rtx insn = NULL_RTX; if (mode == V2DFmode) @@ -7083,6 +7089,53 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx) emit_insn (gen_rtx_SET (target, x)); } +/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX + is variable and also counts by vector element size. */ + +void +rs6000_expand_vector_set_var (rtx target, rtx val, rtx idx) +{ + machine_mode mode = GET_MODE (target); + + gcc_assert (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (idx)); + + gcc_assert (GET_MODE (idx) == E_SImode); + + machine_mode inner_mode = GET_MODE (val); + + rtx tmp = gen_reg_rtx (GET_MODE (idx)); + int width = GET_MODE_SIZE (inner_mode); + + gcc_assert (width >= 1 && width <= 8); + + int shift = exact_log2 (width); + /* Generate the IDX for permute shift, width is the vector element size. + idx = idx * width. */ + emit_insn (gen_ashlsi3 (tmp, idx, GEN_INT (shift))); + + tmp = convert_modes (DImode, SImode, tmp, 1); + + /* lvsr v1,0,idx. */ + rtx pcvr = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsr_reg (pcvr, tmp)); + + /* lvsl v2,0,idx. */ + rtx pcvl = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsl_reg (pcvl, tmp)); + + rtx sub_target = simplify_gen_subreg (V16QImode, target, mode, 0); + + rtx permr + = gen_altivec_vperm_v8hiv16qi (sub_target, sub_target, sub_target, pcvr); + emit_insn (permr); + + rs6000_expand_vector_set (target, val, const0_rtx); + + rtx perml + = gen_altivec_vperm_v8hiv16qi (sub_target, sub_target, sub_target, pcvl); + emit_insn (perml); +} + /* Extract field ELT from VEC into TARGET. */ void diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251-run.c b/gcc/testsuite/gcc.target/powerpc/pr79251-run.c new file mode 100644 index 00000000000..08f69df1146 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79251-run.c @@ -0,0 +1,28 @@ +/* { dg-options "-O2 -maltivec" } */ + +#include +#include +#include "pr79251.h" + +TEST_VEC_INSERT_ALL (test) + +#define run_test(TYPE, num) \ + { \ + vector TYPE v; \ + vector TYPE u = {0x0}; \ + for (long k = 0; k < 16 / sizeof (TYPE); k++) \ + v[k] = 0xaa; \ + for (long k = 0; k < 16 / sizeof (TYPE); k++) \ + { \ + u = test##num (v, 254, k); \ + if (u[k] != (TYPE) 254) \ + __builtin_abort (); \ + } \ + } + +int +main (void) +{ + TEST_VEC_INSERT_ALL (run_test) + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.h b/gcc/testsuite/gcc.target/powerpc/pr79251.h new file mode 100644 index 00000000000..addb067f9ed --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79251.h @@ -0,0 +1,19 @@ + +#define test(TYPE, num) \ + __attribute__ ((noinline, noclone)) \ + vector TYPE test##num (vector TYPE v, TYPE i, signed int n) \ + { \ + return vec_insert (i, v, n); \ + } + +#define TEST_VEC_INSERT_ALL(T) \ + T (char, 0) \ + T (unsigned char, 1) \ + T (short, 2) \ + T (unsigned short, 3) \ + T (int, 4) \ + T (unsigned int, 5) \ + T (long long, 6) \ + T (unsigned long long, 7) \ + T (float, 8) \ + T (double, 9) diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c b/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c new file mode 100644 index 00000000000..ec1cb255888 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -maltivec" } */ + +#include +#include +#include "pr79251.h" + +TEST_VEC_INSERT_ALL (test) + +/* { dg-final { scan-assembler-not {\mstxw\M} } } */ +/* { dg-final { scan-assembler-times {\mlvsl\M} 10 } } */ +/* { dg-final { scan-assembler-times {\mlvsr\M} 10 } } */ +/* { dg-final { scan-assembler-times {\mxxperm\M} 20 } } */ +/* { dg-final { scan-assembler-times {\mxxinsertw\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mvinserth\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvinsertb\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 } } */