From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 16:28:46 +0000 (+0100)
Subject: move reg setup to earlier in test
X-Git-Tag: div_pipeline~601
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b293aca2cc5a8585e064161d77d98a2b7556a92d;p=soc.git

move reg setup to earlier in test
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 6a3f5cb2..877c215e 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -137,6 +137,10 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
+                # set up INT regfile, "direct" write from sim data
+                for i in range(32):
+                    yield core.regs.int.regs[i].reg.eq(test.regs[i])
+
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]
@@ -157,10 +161,6 @@ class TestRunner(FHDLTestCase):
                     yield from set_issue(core, pdecode2, sim)
                     yield Settle()
 
-                    # set up INT regfile, "direct" write from sim data
-                    for i in range(32):
-                        yield core.regs.int.regs[i].reg.eq(test.regs[i])
-
                     yield from wait_for_busy_clear(core)
                     yield core.ivalid_i.eq(0)