From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 23:23:12 +0000 (-0700)
Subject: SigSpec::extend_u0() to return *this
X-Git-Tag: working-ls180~1039^2~362
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b29f26f6c7d880b9a446f6eacfa988c2018a1e30;p=yosys.git

SigSpec::extend_u0() to return *this
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a09f4a0d1..ebb6f5bf6 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3426,7 +3426,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
 	check();
 }
 
-void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
+RTLIL::SigSpec& RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 {
 	cover("kernel.rtlil.sigspec.extend_u0");
 
@@ -3443,6 +3443,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 			append(padding);
 	}
 
+	return *this;
 }
 
 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 82cbfaf28..8d88cc97c 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -776,7 +776,7 @@ public:
 	void append(const RTLIL::SigSpec &signal);
 	void append_bit(const RTLIL::SigBit &bit);
 
-	void extend_u0(int width, bool is_signed = false);
+	RTLIL::SigSpec& extend_u0(int width, bool is_signed = false);
 
 	RTLIL::SigSpec repeat(int num) const;