From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 Mar 2020 18:04:18 +0000 (+0100)
Subject: litex_sim: fix with_uart parameter.
X-Git-Tag: 24jan2021_ls180~607
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b29f443fe51511df908a644a17bc2a8a1f1566cc;p=litex.git

litex_sim: fix with_uart parameter.
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 825a8367..f4146c43 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -168,7 +168,6 @@ class SimSoC(SoCSDRAM):
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
             ident               = "LiteX Simulation", ident_version=True,
-            with_uart           = False,
             l2_reverse          = False,
             **kwargs)
         # CRG --------------------------------------------------------------------------------------
@@ -287,7 +286,7 @@ def main():
     if "cpu_type" in soc_kwargs:
         if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
             cpu_endianness = "big"
-
+    soc_kwargs["with_uart"] = False
     if args.rom_init:
         soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
     if not args.with_sdram: