From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 12:33:13 +0000 (+0200)
Subject: ecp5: ECP5 synthesis fixes
X-Git-Tag: yosys-0.8~55^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2c62ff8efb9650ac3eefab4e7756b7ba303962e;p=yosys.git

ecp5: ECP5 synthesis fixes

Signed-off-by: David Shah <davey1576@gmail.com>
---

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 05d44b9b4..1094c5f8a 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -42,7 +42,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	function integer round_up2;
 		input integer N;
 		begin
-			round_up2 = ((N / 2) + 1) * 2;
+			round_up2 = ((N + 1) / 2) * 2;
 		end
 	endfunction
 
@@ -69,7 +69,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 		);
 
 		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
-		if (i < Y_WIDTH) begin
+		if (i+1 < Y_WIDTH) begin
 			assign CO[i+1] = FCO[i];
 			assign Y[i+1] = Y1[i];
 		end
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 6c53a78eb..1755da24b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -67,10 +67,15 @@ module TRELLIS_RAM16X2 (
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 
-	wire muxwre = (WREMUX == "1") ? 1'b1 :
-							  (WREMUX == "0") ? 1'b0 :
-							  (WREMUX == "INV") ? ~WRE :
-							  WRE;
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
+
 
 	always @(posedge muxwck)
 		if (muxwre)
@@ -108,10 +113,14 @@ module TRELLIS_DPR16X4 (
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 
-	wire muxwre = (WREMUX == "1") ? 1'b1 :
-							  (WREMUX == "0") ? 1'b0 :
-							  (WREMUX == "INV") ? ~WRE :
-							  WRE;
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
 
 	always @(posedge muxwck)
 		if (muxwre)
@@ -167,7 +176,7 @@ module DPR16X4C (
 	integer i;
 	initial begin
 		for (i = 0; i < 15; i = i + 1) begin
-			ram[i] = conv_initval[4*i +: 4];
+			ram[i] <= conv_initval[4*i +: 4];
 		end
 	end
 
@@ -189,10 +198,14 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	parameter SRMODE = "LSR_OVER_CE";
 	parameter REGSET = "RESET";
 
-	wire muxce = (CEMUX == "1") ? 1'b1 :
-	             (CEMUX == "0") ? 1'b0 :
-							 (CEMUX == "INV") ? ~CE :
-							 CE;
+	reg muxce;
+	always @(*)
+		case (CEMUX)
+			"1": muxce = 1'b1;
+			"0": muxce = 1'b0;
+			"INV": muxce = ~CE;
+			default: muxce = CE;
+		endcase
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b54bf4204..76051d1a2 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -172,6 +172,10 @@ struct SynthEcp5Pass : public ScriptPass
 				nodram = true;
 				continue;
 			}
+			if (args[argidx] == "-nomux") {
+				nomux = true;
+				continue;
+			}
 			if (args[argidx] == "-abc2") {
 				abc2 = true;
 				continue;