From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 11 Feb 2020 15:39:37 +0000 (+0100)
Subject: soc: avoid double definition of main_ram
X-Git-Tag: 24jan2021_ls180~677^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2c66b1efd6bd056c26ebd85e9a8ccd2e53e15e0;p=litex.git

soc: avoid double definition of main_ram
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index f20d6ecb..42eab475 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -958,7 +958,7 @@ class LiteXSoC(SoC):
         elif self.with_wishbone:
             # Wishbone Slave SDRAM interface -------------------------------------------------------
             wb_sdram = wishbone.Interface()
-            self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size))
+            self.bus.add_slave("main_ram", wb_sdram)
 
             # L2 Cache -----------------------------------------------------------------------------
             if l2_cache_size != 0: