From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 13:42:26 +0000 (+0100)
Subject: add extra args to ISA in test_pipe_caller.py
X-Git-Tag: div_pipeline~500
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2eb17c54da96fadf5eec01585c9b5983d654efb;p=soc.git

add extra args to ISA in test_pipe_caller.py
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index c8e3153e..1e09224d 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -229,7 +229,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, 0)
+                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                                test.mem, test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))