From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 17 Mar 2015 00:07:44 +0000 (+0100)
Subject: targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC... 
X-Git-Tag: 24jan2021_ls180~2485
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2f32ad124ffd333074f86bc705562910c824630;p=litex.git

targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
---

diff --git a/targets/simple.py b/targets/simple.py
index eb8e183f..7d161711 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,5 +1,6 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
+from migen.genlib.io import CRG
 
 from misoclib.soc import SoC, mem_decoder
 from misoclib.com.liteeth.phy import LiteEthPHY
@@ -12,6 +13,7 @@ class BaseSoC(SoC):
 			with_rom=True,
 			with_main_ram=True, main_ram_size=16*1024,
 			**kwargs)
+		self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 class MiniSoC(BaseSoC):
 	csr_map = {