From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 08:17:39 +0000 (+0100)
Subject: whitespace
X-Git-Tag: ls180-24jan2020~783
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2f9cfbb49c48f49966d1d786c57925bad962b0f;p=ieee754fpu.git

whitespace
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 2c6ec33a..6cb87115 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -71,7 +71,7 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreInputData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
@@ -91,7 +91,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
         """ Assign member signals. """
         print (self, rhs)
         return DivPipeCoreInterstageData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
@@ -110,7 +110,7 @@ class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreOutputData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeBaseStage: