From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Jun 2019 16:50:37 +0000 (-0700)
Subject: Clean up
X-Git-Tag: working-ls180~1237^2~87
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b304744d1506ae5a672639b6baab43c9bce97f00;p=yosys.git

Clean up
---

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 53a89e8a3..b504d51e2 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -70,6 +70,8 @@ module \$lut (A, Y);
     parameter WIDTH = 0;
     parameter LUT = 0;
 
+    input [WIDTH-1:0] A;
+    output Y;
 
     // Need to swap input ordering, and fix init accordingly,
     // to match ABC's expectation of LUT inputs in non-decreasing
@@ -86,19 +88,15 @@ module \$lut (A, Y);
     endfunction
 
     function [2**P_WIDTH-1:0] permute_init;
-        input [2**P_WIDTH-1:0] orig;
         integer i;
         begin
             permute_init = 0;
             for (i = 0; i < 2**P_WIDTH; i = i + 1)
-                permute_init[i] = orig[permute_index(i)];
+                permute_init[i] = LUT[permute_index(i)];
         end
     endfunction
 
-    parameter [2**P_WIDTH-1:0] P_LUT = permute_init(LUT);
-
-    input [WIDTH-1:0] A;
-    output Y;
+    parameter [2**P_WIDTH-1:0] P_LUT = permute_init();
 
     generate
         if (WIDTH == 1) begin