From: Florent Kermarrec Date: Mon, 2 Mar 2015 07:24:51 +0000 (+0100) Subject: sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it X-Git-Tag: 24jan2021_ls180~2541 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b305b7828a98cc5dd72925a8f4bde94bb58b460a;p=litex.git sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it --- diff --git a/misoclib/com/liteusb/frontend/dma.py b/misoclib/com/liteusb/frontend/dma.py index a8e1ef99..6aff0f0c 100644 --- a/misoclib/com/liteusb/frontend/dma.py +++ b/misoclib/com/liteusb/frontend/dma.py @@ -1,11 +1,13 @@ from migen.fhdl.std import * from migen.flow.actor import * from migen.flow.network import * -from migen.actorlib import dma_lasmi, structuring, spi +from migen.actorlib import structuring, spi from migen.bank.description import * from migen.bank.eventmanager import * from migen.genlib.record import Record +from misoclib.mem.sdram.frontend import dma_lasmi + from liteusb.ftdi.std import * class FtdiDMAWriter(Module, AutoCSR): diff --git a/misoclib/mem/sdram/bus/wishbone2lasmi.py b/misoclib/mem/sdram/bus/wishbone2lasmi.py deleted file mode 100644 index 91abe5c3..00000000 --- a/misoclib/mem/sdram/bus/wishbone2lasmi.py +++ /dev/null @@ -1,168 +0,0 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bank.description import * -from migen.genlib.fsm import FSM, NextState -from migen.genlib.misc import split, displacer, chooser -from migen.genlib.record import Record, layout_len - -# cachesize (in 32-bit words) is the size of the data store, must be a power of 2 -class WB2LASMI(Module, AutoCSR): - def __init__(self, cachesize, lasmim): - self._cachesize = CSRStatus(8, reset=log2_int(cachesize)) - self.wishbone = wishbone.Interface() - - ### - - data_width = flen(self.wishbone.dat_r) - if lasmim.dw > data_width and (lasmim.dw % data_width) != 0: - raise ValueError("LASMI data width must be a multiple of {dw}".format(dw=data_width)) - if lasmim.dw < data_width and (data_width % lasmim.dw) != 0: - raise ValueError("WISHBONE data width must be a multiple of {dw}".format(dw=lasmim.dw)) - - # Split address: - # TAG | LINE NUMBER | LINE OFFSET - offsetbits = log2_int(max(lasmim.dw//data_width, 1)) - addressbits = lasmim.aw + offsetbits - linebits = log2_int(cachesize) - offsetbits - tagbits = addressbits - linebits - wordbits = log2_int(max(data_width//lasmim.dw, 1)) - adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits) - word = Signal(wordbits) if wordbits else None - - # Data memory - data_mem = Memory(lasmim.dw*2**wordbits, 2**linebits) - data_port = data_mem.get_port(write_capable=True, we_granularity=8) - self.specials += data_mem, data_port - - write_from_lasmi = Signal() - write_to_lasmi = Signal() - if adr_offset is None: - adr_offset_r = None - else: - adr_offset_r = Signal(offsetbits) - self.sync += adr_offset_r.eq(adr_offset) - - self.comb += [ - data_port.adr.eq(adr_line), - If(write_from_lasmi, - displacer(lasmim.dat_r, word, data_port.dat_w), - displacer(Replicate(1, lasmim.dw//8), word, data_port.we) - ).Else( - data_port.dat_w.eq(Replicate(self.wishbone.dat_w, max(lasmim.dw//data_width, 1))), - If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack, - displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True) - ) - ), - If(write_to_lasmi, - chooser(data_port.dat_r, word, lasmim.dat_w), - lasmim.dat_we.eq(2**(lasmim.dw//8)-1) - ), - chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True) - ] - - - # Tag memory - tag_layout = [("tag", tagbits), ("dirty", 1)] - tag_mem = Memory(layout_len(tag_layout), 2**linebits) - tag_port = tag_mem.get_port(write_capable=True) - self.specials += tag_mem, tag_port - tag_do = Record(tag_layout) - tag_di = Record(tag_layout) - self.comb += [ - tag_do.raw_bits().eq(tag_port.dat_r), - tag_port.dat_w.eq(tag_di.raw_bits()) - ] - - self.comb += [ - tag_port.adr.eq(adr_line), - tag_di.tag.eq(adr_tag) - ] - if word is not None: - self.comb += lasmim.adr.eq(Cat(word, adr_line, tag_do.tag)) - else: - self.comb += lasmim.adr.eq(Cat(adr_line, tag_do.tag)) - - # Lasmim word computation, word_clr and word_inc will be simplified - # at synthesis when wordbits=0 - word_clr = Signal() - word_inc = Signal() - if word is not None: - self.sync += \ - If(word_clr, - word.eq(0), - ).Elif(word_inc, - word.eq(word+1) - ) - - def word_is_last(word): - if word is not None: - return word == 2**wordbits-1 - else: - return 1 - - # Control FSM - assert(lasmim.write_latency >= 1 and lasmim.read_latency >= 1) - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - - - fsm.act("IDLE", - If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT")) - ) - fsm.act("TEST_HIT", - word_clr.eq(1), - If(tag_do.tag == adr_tag, - self.wishbone.ack.eq(1), - If(self.wishbone.we, - tag_di.dirty.eq(1), - tag_port.we.eq(1) - ), - NextState("IDLE") - ).Else( - If(tag_do.dirty, - NextState("EVICT_REQUEST") - ).Else( - NextState("REFILL_WRTAG") - ) - ) - ) - - fsm.act("EVICT_REQUEST", - lasmim.stb.eq(1), - lasmim.we.eq(1), - If(lasmim.req_ack, NextState("EVICT_WAIT_DATA_ACK")) - ) - fsm.act("EVICT_WAIT_DATA_ACK", - If(lasmim.dat_w_ack, NextState("EVICT_DATA")) - ) - fsm.act("EVICT_DATA", - write_to_lasmi.eq(1), - word_inc.eq(1), - If(word_is_last(word), - NextState("REFILL_WRTAG"), - ).Else( - NextState("EVICT_REQUEST") - ) - ) - - fsm.act("REFILL_WRTAG", - # Write the tag first to set the LASMI address - tag_port.we.eq(1), - word_clr.eq(1), - NextState("REFILL_REQUEST") - ) - fsm.act("REFILL_REQUEST", - lasmim.stb.eq(1), - If(lasmim.req_ack, NextState("REFILL_DATA")) - ) - fsm.act("REFILL_DATA", - If(lasmim.dat_r_ack, - write_from_lasmi.eq(1), - word_inc.eq(1), - If(word_is_last(word), - NextState("TEST_HIT"), - ).Else( - NextState("REFILL_REQUEST") - ) - ) - ) diff --git a/misoclib/mem/sdram/frontend/__init__.py b/misoclib/mem/sdram/frontend/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/misoclib/mem/sdram/frontend/dma_lasmi.py b/misoclib/mem/sdram/frontend/dma_lasmi.py new file mode 100644 index 00000000..de31bda7 --- /dev/null +++ b/misoclib/mem/sdram/frontend/dma_lasmi.py @@ -0,0 +1,89 @@ +from migen.fhdl.std import * +from migen.flow.actor import * +from migen.genlib.fifo import SyncFIFO + +class Reader(Module): + def __init__(self, lasmim, fifo_depth=None): + self.address = Sink([("a", lasmim.aw)]) + self.data = Source([("d", lasmim.dw)]) + self.busy = Signal() + + ### + + if fifo_depth is None: + fifo_depth = lasmim.req_queue_size + lasmim.read_latency + 2 + + # request issuance + request_enable = Signal() + request_issued = Signal() + + self.comb += [ + lasmim.we.eq(0), + lasmim.stb.eq(self.address.stb & request_enable), + lasmim.adr.eq(self.address.a), + self.address.ack.eq(lasmim.req_ack & request_enable), + request_issued.eq(lasmim.stb & lasmim.req_ack) + ] + + # FIFO reservation level counter + # incremented when data is planned to be queued + # decremented when data is dequeued + data_dequeued = Signal() + rsv_level = Signal(max=fifo_depth+1) + self.sync += [ + If(request_issued, + If(~data_dequeued, rsv_level.eq(rsv_level + 1)) + ).Elif(data_dequeued, + rsv_level.eq(rsv_level - 1) + ) + ] + self.comb += [ + self.busy.eq(rsv_level != 0), + request_enable.eq(rsv_level != fifo_depth) + ] + + # FIFO + fifo = SyncFIFO(lasmim.dw, fifo_depth) + self.submodules += fifo + + self.comb += [ + fifo.din.eq(lasmim.dat_r), + fifo.we.eq(lasmim.dat_r_ack), + + self.data.stb.eq(fifo.readable), + fifo.re.eq(self.data.ack), + self.data.d.eq(fifo.dout), + data_dequeued.eq(self.data.stb & self.data.ack) + ] + + +class Writer(Module): + def __init__(self, lasmim, fifo_depth=None): + self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)]) + self.busy = Signal() + + ### + + if fifo_depth is None: + fifo_depth = lasmim.req_queue_size + lasmim.write_latency + 2 + + fifo = SyncFIFO(lasmim.dw, fifo_depth) + self.submodules += fifo + + self.comb += [ + lasmim.we.eq(1), + lasmim.stb.eq(fifo.writable & self.address_data.stb), + lasmim.adr.eq(self.address_data.a), + self.address_data.ack.eq(fifo.writable & lasmim.req_ack), + fifo.we.eq(self.address_data.stb & lasmim.req_ack), + fifo.din.eq(self.address_data.d) + ] + + self.comb += [ + fifo.re.eq(lasmim.dat_w_ack), + If(data_valid, + lasmim.dat_we.eq(2**(lasmim.dw//8)-1), + lasmim.dat_w.eq(fifo.dout) + ), + self.busy.eq(fifo.readable) + ] diff --git a/misoclib/mem/sdram/frontend/memtest.py b/misoclib/mem/sdram/frontend/memtest.py new file mode 100644 index 00000000..7627d817 --- /dev/null +++ b/misoclib/mem/sdram/frontend/memtest.py @@ -0,0 +1,113 @@ +from migen.fhdl.std import * +from migen.genlib.misc import optree +from migen.bank.description import * +from migen.actorlib.spi import * + +from misoclib.mem.sdram.frontend import dma_lasmi + +@DecorateModule(InsertReset) +@DecorateModule(InsertCE) +class LFSR(Module): + def __init__(self, n_out, n_state=31, taps=[27, 30]): + self.o = Signal(n_out) + + ### + + state = Signal(n_state) + curval = [state[i] for i in range(n_state)] + curval += [0]*(n_out - n_state) + for i in range(n_out): + nv = ~optree("^", [curval[tap] for tap in taps]) + curval.insert(0, nv) + curval.pop() + + self.sync += [ + state.eq(Cat(*curval[:n_state])), + self.o.eq(Cat(*curval)) + ] + +memtest_magic = 0x361f + +class MemtestWriter(Module): + def __init__(self, lasmim): + self._magic = CSRStatus(16) + self._reset = CSR() + self._shoot = CSR() + self.submodules._dma = DMAWriteController(dma_lasmi.Writer(lasmim), MODE_EXTERNAL) + + ### + + self.comb += self._magic.status.eq(memtest_magic) + + lfsr = LFSR(lasmim.dw) + self.submodules += lfsr + self.comb += lfsr.reset.eq(self._reset.re) + + en = Signal() + en_counter = Signal(lasmim.aw) + self.comb += en.eq(en_counter != 0) + self.sync += [ + If(self._shoot.re, + en_counter.eq(self._dma.length) + ).Elif(lfsr.ce, + en_counter.eq(en_counter - 1) + ) + ] + + self.comb += [ + self._dma.trigger.eq(self._shoot.re), + self._dma.data.stb.eq(en), + lfsr.ce.eq(en & self._dma.data.ack), + self._dma.data.d.eq(lfsr.o) + ] + + def get_csrs(self): + return [self._magic, self._reset, self._shoot] + self._dma.get_csrs() + +class MemtestReader(Module): + def __init__(self, lasmim): + self._magic = CSRStatus(16) + self._reset = CSR() + self._error_count = CSRStatus(lasmim.aw) + self.submodules._dma = DMAReadController(dma_lasmi.Reader(lasmim), MODE_SINGLE_SHOT) + + ### + + self.comb += self._magic.status.eq(memtest_magic) + + lfsr = LFSR(lasmim.dw) + self.submodules += lfsr + self.comb += lfsr.reset.eq(self._reset.re) + + self.comb += [ + lfsr.ce.eq(self._dma.data.stb), + self._dma.data.ack.eq(1) + ] + err_cnt = self._error_count.status + self.sync += [ + If(self._reset.re, + err_cnt.eq(0) + ).Elif(self._dma.data.stb, + If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1)) + ) + ] + + def get_csrs(self): + return [self._magic, self._reset, self._error_count] + self._dma.get_csrs() + +class _LFSRTB(Module): + def __init__(self, *args, **kwargs): + self.submodules.dut = LFSR(*args, **kwargs) + self.comb += self.dut.ce.eq(1) + + def do_simulation(self, selfp): + print("{0:032x}".format(selfp.dut.o)) + +if __name__ == "__main__": + from migen.fhdl import verilog + from migen.sim.generic import run_simulation + + lfsr = LFSR(3, 4, [3, 2]) + print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o})) + + run_simulation(_LFSRTB(128), ncycles=20) diff --git a/misoclib/mem/sdram/frontend/wishbone2lasmi.py b/misoclib/mem/sdram/frontend/wishbone2lasmi.py new file mode 100644 index 00000000..91abe5c3 --- /dev/null +++ b/misoclib/mem/sdram/frontend/wishbone2lasmi.py @@ -0,0 +1,168 @@ +from migen.fhdl.std import * +from migen.bus import wishbone +from migen.bank.description import * +from migen.genlib.fsm import FSM, NextState +from migen.genlib.misc import split, displacer, chooser +from migen.genlib.record import Record, layout_len + +# cachesize (in 32-bit words) is the size of the data store, must be a power of 2 +class WB2LASMI(Module, AutoCSR): + def __init__(self, cachesize, lasmim): + self._cachesize = CSRStatus(8, reset=log2_int(cachesize)) + self.wishbone = wishbone.Interface() + + ### + + data_width = flen(self.wishbone.dat_r) + if lasmim.dw > data_width and (lasmim.dw % data_width) != 0: + raise ValueError("LASMI data width must be a multiple of {dw}".format(dw=data_width)) + if lasmim.dw < data_width and (data_width % lasmim.dw) != 0: + raise ValueError("WISHBONE data width must be a multiple of {dw}".format(dw=lasmim.dw)) + + # Split address: + # TAG | LINE NUMBER | LINE OFFSET + offsetbits = log2_int(max(lasmim.dw//data_width, 1)) + addressbits = lasmim.aw + offsetbits + linebits = log2_int(cachesize) - offsetbits + tagbits = addressbits - linebits + wordbits = log2_int(max(data_width//lasmim.dw, 1)) + adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits) + word = Signal(wordbits) if wordbits else None + + # Data memory + data_mem = Memory(lasmim.dw*2**wordbits, 2**linebits) + data_port = data_mem.get_port(write_capable=True, we_granularity=8) + self.specials += data_mem, data_port + + write_from_lasmi = Signal() + write_to_lasmi = Signal() + if adr_offset is None: + adr_offset_r = None + else: + adr_offset_r = Signal(offsetbits) + self.sync += adr_offset_r.eq(adr_offset) + + self.comb += [ + data_port.adr.eq(adr_line), + If(write_from_lasmi, + displacer(lasmim.dat_r, word, data_port.dat_w), + displacer(Replicate(1, lasmim.dw//8), word, data_port.we) + ).Else( + data_port.dat_w.eq(Replicate(self.wishbone.dat_w, max(lasmim.dw//data_width, 1))), + If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack, + displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True) + ) + ), + If(write_to_lasmi, + chooser(data_port.dat_r, word, lasmim.dat_w), + lasmim.dat_we.eq(2**(lasmim.dw//8)-1) + ), + chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True) + ] + + + # Tag memory + tag_layout = [("tag", tagbits), ("dirty", 1)] + tag_mem = Memory(layout_len(tag_layout), 2**linebits) + tag_port = tag_mem.get_port(write_capable=True) + self.specials += tag_mem, tag_port + tag_do = Record(tag_layout) + tag_di = Record(tag_layout) + self.comb += [ + tag_do.raw_bits().eq(tag_port.dat_r), + tag_port.dat_w.eq(tag_di.raw_bits()) + ] + + self.comb += [ + tag_port.adr.eq(adr_line), + tag_di.tag.eq(adr_tag) + ] + if word is not None: + self.comb += lasmim.adr.eq(Cat(word, adr_line, tag_do.tag)) + else: + self.comb += lasmim.adr.eq(Cat(adr_line, tag_do.tag)) + + # Lasmim word computation, word_clr and word_inc will be simplified + # at synthesis when wordbits=0 + word_clr = Signal() + word_inc = Signal() + if word is not None: + self.sync += \ + If(word_clr, + word.eq(0), + ).Elif(word_inc, + word.eq(word+1) + ) + + def word_is_last(word): + if word is not None: + return word == 2**wordbits-1 + else: + return 1 + + # Control FSM + assert(lasmim.write_latency >= 1 and lasmim.read_latency >= 1) + fsm = FSM(reset_state="IDLE") + self.submodules += fsm + + + fsm.act("IDLE", + If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT")) + ) + fsm.act("TEST_HIT", + word_clr.eq(1), + If(tag_do.tag == adr_tag, + self.wishbone.ack.eq(1), + If(self.wishbone.we, + tag_di.dirty.eq(1), + tag_port.we.eq(1) + ), + NextState("IDLE") + ).Else( + If(tag_do.dirty, + NextState("EVICT_REQUEST") + ).Else( + NextState("REFILL_WRTAG") + ) + ) + ) + + fsm.act("EVICT_REQUEST", + lasmim.stb.eq(1), + lasmim.we.eq(1), + If(lasmim.req_ack, NextState("EVICT_WAIT_DATA_ACK")) + ) + fsm.act("EVICT_WAIT_DATA_ACK", + If(lasmim.dat_w_ack, NextState("EVICT_DATA")) + ) + fsm.act("EVICT_DATA", + write_to_lasmi.eq(1), + word_inc.eq(1), + If(word_is_last(word), + NextState("REFILL_WRTAG"), + ).Else( + NextState("EVICT_REQUEST") + ) + ) + + fsm.act("REFILL_WRTAG", + # Write the tag first to set the LASMI address + tag_port.we.eq(1), + word_clr.eq(1), + NextState("REFILL_REQUEST") + ) + fsm.act("REFILL_REQUEST", + lasmim.stb.eq(1), + If(lasmim.req_ack, NextState("REFILL_DATA")) + ) + fsm.act("REFILL_DATA", + If(lasmim.dat_r_ack, + write_from_lasmi.eq(1), + word_inc.eq(1), + If(word_is_last(word), + NextState("TEST_HIT"), + ).Else( + NextState("REFILL_REQUEST") + ) + ) + ) diff --git a/misoclib/mem/sdram/lasmicon/test/lasmicon_df.py b/misoclib/mem/sdram/lasmicon/test/lasmicon_df.py index aff7288f..7f2f886b 100644 --- a/misoclib/mem/sdram/lasmicon/test/lasmicon_df.py +++ b/misoclib/mem/sdram/lasmicon/test/lasmicon_df.py @@ -1,9 +1,9 @@ from migen.fhdl.std import * -from migen.actorlib import dma_lasmi from migen.sim.generic import run_simulation from misoclib.mem.sdram.bus import lasmibus from misoclib.mem.sdram.lasmicon import * +from misoclib.mem.sdram.frontend import dma_lasmi from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/mem/sdram/lasmicon/test/lasmicon_wb.py b/misoclib/mem/sdram/lasmicon/test/lasmicon_wb.py index 63a7b073..53fc7b87 100644 --- a/misoclib/mem/sdram/lasmicon/test/lasmicon_wb.py +++ b/misoclib/mem/sdram/lasmicon/test/lasmicon_wb.py @@ -3,8 +3,9 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.bus import lasmibus, wishbone2lasmi +from misoclib.mem.sdram.bus import lasmibus from misoclib.mem.sdram.lasmicon import * +from misoclib.mem.sdram.frontend import wishbone2lasmi from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/mem/sdram/memtest/__init__.py b/misoclib/mem/sdram/memtest/__init__.py deleted file mode 100644 index 312bea50..00000000 --- a/misoclib/mem/sdram/memtest/__init__.py +++ /dev/null @@ -1,112 +0,0 @@ -from migen.fhdl.std import * -from migen.genlib.misc import optree -from migen.bank.description import * -from migen.actorlib import dma_lasmi -from migen.actorlib.spi import * - -@DecorateModule(InsertReset) -@DecorateModule(InsertCE) -class LFSR(Module): - def __init__(self, n_out, n_state=31, taps=[27, 30]): - self.o = Signal(n_out) - - ### - - state = Signal(n_state) - curval = [state[i] for i in range(n_state)] - curval += [0]*(n_out - n_state) - for i in range(n_out): - nv = ~optree("^", [curval[tap] for tap in taps]) - curval.insert(0, nv) - curval.pop() - - self.sync += [ - state.eq(Cat(*curval[:n_state])), - self.o.eq(Cat(*curval)) - ] - -memtest_magic = 0x361f - -class MemtestWriter(Module): - def __init__(self, lasmim): - self._magic = CSRStatus(16) - self._reset = CSR() - self._shoot = CSR() - self.submodules._dma = DMAWriteController(dma_lasmi.Writer(lasmim), MODE_EXTERNAL) - - ### - - self.comb += self._magic.status.eq(memtest_magic) - - lfsr = LFSR(lasmim.dw) - self.submodules += lfsr - self.comb += lfsr.reset.eq(self._reset.re) - - en = Signal() - en_counter = Signal(lasmim.aw) - self.comb += en.eq(en_counter != 0) - self.sync += [ - If(self._shoot.re, - en_counter.eq(self._dma.length) - ).Elif(lfsr.ce, - en_counter.eq(en_counter - 1) - ) - ] - - self.comb += [ - self._dma.trigger.eq(self._shoot.re), - self._dma.data.stb.eq(en), - lfsr.ce.eq(en & self._dma.data.ack), - self._dma.data.d.eq(lfsr.o) - ] - - def get_csrs(self): - return [self._magic, self._reset, self._shoot] + self._dma.get_csrs() - -class MemtestReader(Module): - def __init__(self, lasmim): - self._magic = CSRStatus(16) - self._reset = CSR() - self._error_count = CSRStatus(lasmim.aw) - self.submodules._dma = DMAReadController(dma_lasmi.Reader(lasmim), MODE_SINGLE_SHOT) - - ### - - self.comb += self._magic.status.eq(memtest_magic) - - lfsr = LFSR(lasmim.dw) - self.submodules += lfsr - self.comb += lfsr.reset.eq(self._reset.re) - - self.comb += [ - lfsr.ce.eq(self._dma.data.stb), - self._dma.data.ack.eq(1) - ] - err_cnt = self._error_count.status - self.sync += [ - If(self._reset.re, - err_cnt.eq(0) - ).Elif(self._dma.data.stb, - If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1)) - ) - ] - - def get_csrs(self): - return [self._magic, self._reset, self._error_count] + self._dma.get_csrs() - -class _LFSRTB(Module): - def __init__(self, *args, **kwargs): - self.submodules.dut = LFSR(*args, **kwargs) - self.comb += self.dut.ce.eq(1) - - def do_simulation(self, selfp): - print("{0:032x}".format(selfp.dut.o)) - -if __name__ == "__main__": - from migen.fhdl import verilog - from migen.sim.generic import run_simulation - - lfsr = LFSR(3, 4, [3, 2]) - print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o})) - - run_simulation(_LFSRTB(128), ncycles=20) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 3dead170..3e93fdb4 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -1,10 +1,10 @@ from migen.fhdl.std import * from migen.bus import wishbone, csr -from misoclib.mem.sdram.bus import dfi, lasmibus, wishbone2lasmi +from misoclib.mem.sdram.bus import dfi, lasmibus from misoclib.mem.sdram import minicon, lasmicon from misoclib.mem.sdram import dfii -from misoclib.mem.sdram import memtest +from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi from misoclib.soc import SoC, mem_decoder class SDRAMSoC(SoC): diff --git a/misoclib/video/dvisampler/debug.py b/misoclib/video/dvisampler/debug.py index de1d6cac..bb52d07a 100644 --- a/misoclib/video/dvisampler/debug.py +++ b/misoclib/video/dvisampler/debug.py @@ -2,8 +2,9 @@ from migen.fhdl.std import * from migen.genlib.fifo import AsyncFIFO from migen.genlib.record import layout_len from migen.bank.description import AutoCSR -from migen.actorlib import structuring, dma_lasmi, spi +from migen.actorlib import structuring, spi +from misoclib.mem.sdram.frontend import dma_lasmi from misoclib.video.dvisampler.edid import EDID from misoclib.video.dvisampler.clocking import Clocking from misoclib.video.dvisampler.datacapture import DataCapture diff --git a/misoclib/video/dvisampler/dma.py b/misoclib/video/dvisampler/dma.py index 3bcb6e35..68fc655e 100644 --- a/misoclib/video/dvisampler/dma.py +++ b/misoclib/video/dvisampler/dma.py @@ -3,7 +3,8 @@ from migen.genlib.fsm import FSM, NextState from migen.bank.description import * from migen.bank.eventmanager import * from migen.flow.actor import * -from migen.actorlib import dma_lasmi + +from misoclib.mem.sdram.frontend import dma_lasmi # Slot status: EMPTY=0 LOADED=1 PENDING=2 class _Slot(Module, AutoCSR): diff --git a/misoclib/video/framebuffer/__init__.py b/misoclib/video/framebuffer/__init__.py index f2766bdb..433812cf 100644 --- a/misoclib/video/framebuffer/__init__.py +++ b/misoclib/video/framebuffer/__init__.py @@ -2,8 +2,9 @@ from migen.fhdl.std import * from migen.flow.network import * from migen.flow import plumbing from migen.bank.description import AutoCSR -from migen.actorlib import dma_lasmi, structuring, misc +from migen.actorlib import structuring, misc +from misoclib.mem.sdram.frontend import dma_lasmi from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG from misoclib.video.framebuffer.phy import Driver