From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Oct 2018 08:09:21 +0000 (+0100)
Subject: swap #ifdef USING_NOREGS so that it is possible to redefine set_pc
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3242f2a7a483bbb4bf54f8045730e6dcc012fbf;p=riscv-isa-sim.git

swap #ifdef USING_NOREGS so that it is possible to redefine set_pc

to avoid having to modify the branch instructions the set_pc macro will
be #undefd and redefined to modify the predication target
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index db05253..9869707 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -13,7 +13,10 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   // and create an sv-variant.  also an opportunity to pass
   // in a stack of other things that are needed.
   insn_bits_t bits = s_insn.bits();
-#ifndef USING_NOREGS
+#ifdef USING_NOREGS
+  insn_t insn(bits);
+  #include INCLUDEFILE
+#else
   int vlen = 0;
   if (p->get_state()->prv == 0) { // XXX HACK - disable in supervisor mode
     vlen = p->get_state()->vl;
@@ -173,9 +176,6 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #ifdef INSN_CATEGORY_TWINPREDICATION
   *src_offs = 0;
 #endif
-#else
-  insn_t insn(bits);
-  #include INCLUDEFILE
 #endif
   trace_opcode(p, INSNCODE, insn);
   return npc;