From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 3 Aug 2019 09:49:31 +0000 (+0100)
Subject: give names to muxer submodules
X-Git-Tag: ls180-24jan2020~554
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3258052150f290f97093bb7b7b861761adc3bc3;p=ieee754fpu.git

give names to muxer submodules
---

diff --git a/src/nmutil/multipipe.py b/src/nmutil/multipipe.py
index 14d532d3..c0d9127c 100644
--- a/src/nmutil/multipipe.py
+++ b/src/nmutil/multipipe.py
@@ -180,7 +180,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
         m = MultiOutControlBase.elaborate(self, platform)
 
         if hasattr(self.n_mux, "elaborate"): # TODO: identify submodule?
-            m.submodules += self.n_mux
+            m.submodules.n_mux = self.n_mux
 
         # need buffer register conforming to *input* spec
         r_data = _spec(self.stage.ispec, 'r_data') # input type
@@ -260,7 +260,7 @@ class CombMultiInPipeline(MultiInControlBase):
     def elaborate(self, platform):
         m = MultiInControlBase.elaborate(self, platform)
 
-        m.submodules += self.p_mux
+        m.submodules.p_mux = self.p_mux
 
         # need an array of buffer registers conforming to *input* spec
         r_data = []