From: Florent Kermarrec Date: Sat, 28 Feb 2015 22:08:50 +0000 (+0100) Subject: liteeth: create example design derived from SoC that can be used on all targets with... X-Git-Tag: 24jan2021_ls180~2557 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b32a0e6f9efdca6510d83430005e654beb53650a;p=litex.git liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins --- diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py index 3dd0b45f..82033189 100644 --- a/misoclib/com/liteeth/example_designs/make.py +++ b/misoclib/com/liteeth/example_designs/make.py @@ -51,17 +51,20 @@ if __name__ == "__main__": args = _get_args() # create top-level Core object - target_module = _import("misoclib.com.liteeth.example_designs.targets", args.target) + target_module = _import("targets", args.target) if args.sub_target: top_class = getattr(target_module, args.sub_target) else: top_class = target_module.default_subtarget if args.platform is None: - platform_name = top_class.default_platform + if hasattr(top_class, "default_platform"): + platform_name = top_class.default_platform + else: + raise ValueError("Target has no default platform, specify a platform with -p your_platform") else: platform_name = args.platform - platform_module = _import("misoclib.com.liteeth.example_designs.platforms", platform_name) + platform_module = _import("mibuild.platforms", platform_name) platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) platform = platform_module.Platform(**platform_kwargs) diff --git a/misoclib/com/liteeth/example_designs/platforms/kc705.py b/misoclib/com/liteeth/example_designs/platforms/kc705.py deleted file mode 100644 index fcc0ee2c..00000000 --- a/misoclib/com/liteeth/example_designs/platforms/kc705.py +++ /dev/null @@ -1,112 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG -from mibuild.xilinx.common import CRG_DS -from mibuild.xilinx.ise import XilinxISEPlatform -from mibuild.xilinx.vivado import XilinxVivadoPlatform -from mibuild.xilinx.programmer import * - -_io = [ - ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), - ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), - ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), - ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), - ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")), - ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), - ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), - ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), - - ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), - - ("clk200", 0, - Subsignal("p", Pins("AD12"), IOStandard("LVDS")), - Subsignal("n", Pins("AD11"), IOStandard("LVDS")) - ), - - ("clk156", 0, - Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), - Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) - ), - - - ("serial", 0, - Subsignal("cts", Pins("L27")), - Subsignal("rts", Pins("K23")), - Subsignal("tx", Pins("K24")), - Subsignal("rx", Pins("M19")), - IOStandard("LVCMOS25") - ), - - ("eth_clocks", 0, - Subsignal("tx", Pins("M28")), - Subsignal("gtx", Pins("K30")), - Subsignal("rx", Pins("U27")), - IOStandard("LVCMOS25") - ), - ("eth", 0, - Subsignal("rst_n", Pins("L20")), - Subsignal("int_n", Pins("N30")), - Subsignal("mdio", Pins("J21")), - Subsignal("mdc", Pins("R23")), - Subsignal("dv", Pins("R28")), - Subsignal("rx_er", Pins("V26")), - Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")), - Subsignal("tx_en", Pins("M27")), - Subsignal("tx_er", Pins("N29")), - Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), - IOStandard("LVCMOS25") - ), - -] - -def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs): - if toolchain == "ise": - xilinx_platform = XilinxISEPlatform - elif toolchain == "vivado": - xilinx_platform = XilinxVivadoPlatform - else: - raise ValueError - - class RealPlatform(xilinx_platform): - bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" - - def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset")): - xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory) - - def create_programmer(self): - if programmer == "xc3sprog": - return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit") - elif programmer == "vivado": - return VivadoProgrammer() - else: - raise ValueError - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk156").p, 6.4) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("clk200").p, 5.0) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) - except ConstraintError: - pass - self.add_platform_command(""" -create_clock -name sys_clk -period 6 [get_nets sys_clk] -create_clock -name eth_rx_clk -period 8 [get_nets eth_rx_clk] -create_clock -name eth_tx_clk -period 8 [get_nets eth_tx_clk] - -set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk] -set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk] -set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk] -set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] - -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -""") - - return RealPlatform(*args, **kwargs) diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index ef099ade..5ab995fa 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -1,14 +1,7 @@ -import os - -from migen.bank import csrgen -from migen.bus import wishbone, csr -from migen.bus import wishbone2csr -from migen.genlib.cdc import * -from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.bus import wishbone from migen.bank.description import * -from targets import * - +from misoclib.soc import SoC from misoclib.tools.litescope.common import * from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB from misoclib.tools.litescope.frontend.la import LiteScopeLA @@ -20,97 +13,20 @@ from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII from misoclib.com.liteeth.core import LiteEthUDPIPCore class _CRG(Module): - def __init__(self, platform): + def __init__(self, clk_in): self.clock_domains.cd_sys = ClockDomain() - self.reset = Signal() - - clk200 = platform.request("clk200") - clk200_se = Signal() - self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se) - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1GHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, - p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 166MHz - p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, - - p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=, - - p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=, + self.clock_domains.cd_por = ClockDomain(reset_less=True) - p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=, - - p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4= - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset), + # Power on Reset (vendor agnostic) + rst_n = Signal() + self.sync.por += rst_n.eq(1) + self.comb += [ + self.cd_sys.clk.eq(clk_in), + self.cd_por.clk.eq(clk_in), + self.cd_sys.rst.eq(~rst_n) ] -class SoC(Module): - csr_base = 0x00000000 - csr_data_width = 32 - csr_map = { - "bridge": 0, - "identifier": 1, - } - interrupt_map = {} - cpu_type = None - def __init__(self, platform, clk_freq): - self.clk_freq = clk_freq - # UART <--> Wishbone bridge - self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600) - - # CSR bridge 0x00000000 (shadow @0x00000000) - self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) - self._wb_masters = [self.bridge.wishbone] - self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] - self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) - - # CSR - self.submodules.identifier = Identifier(0, int(clk_freq), 0) - - def add_wb_master(self, wbm): - if self.finalized: - raise FinalizeError - self._wb_masters.append(wbm) - - def add_wb_slave(self, address_decoder, interface): - if self.finalized: - raise FinalizeError - self._wb_slaves.append((address_decoder, interface)) - - def add_cpu_memory_region(self, name, origin, length): - self.cpu_memory_regions.append((name, origin, length)) - - def add_cpu_csr_region(self, name, origin, busword, obj): - self.cpu_csr_regions.append((name, origin, busword, obj)) - - def do_finalize(self): - # Wishbone - self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, - self._wb_slaves, register=True) - - # CSR - self.submodules.csrbankarray = csrgen.BankArray(self, - lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], - data_width=self.csr_data_width) - self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) - for name, csrs, mapaddr, rmap in self.csrbankarray.banks: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) - for name, memory, mapaddr, mmap in self.csrbankarray.srams: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) - class BaseSoC(SoC, AutoCSR): - default_platform = "kc705" csr_map = { "phy": 11, "core": 12 @@ -119,8 +35,17 @@ class BaseSoC(SoC, AutoCSR): def __init__(self, platform, clk_freq=166*1000000, mac_address=0x10e2d5000000, ip_address="192.168.1.40"): - SoC.__init__(self, platform, clk_freq) - self.submodules.crg = _CRG(platform) + clk_freq = int((1/(platform.default_clk_period))*1000000000) + self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200) + SoC.__init__(self, platform, clk_freq, self.uart2wb, + with_cpu=False, + with_csr=True, csr_data_width=32, + with_uart=False, + with_identifier=True, + with_timer=False + ) + clk_in = platform.request(platform.default_clk_name) + self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p) # wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py index 572a1d0e..3d884d0a 100644 --- a/misoclib/tools/litescope/example_designs/targets/simple.py +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -37,7 +37,8 @@ class LiteScopeSoC(SoC, AutoCSR): with_identifier=True, with_timer=False ) - self.submodules.crg = _CRG(platform.request(platform.default_clk_name)) + clk_in = platform.request(platform.default_clk_name) + self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p) self.submodules.io = LiteScopeIO(8) for i in range(8): diff --git a/targets/simple.py b/targets/simple.py index 32c72ffb..8e2c47b3 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -24,6 +24,7 @@ class SimpleSoC(SoC): with_rom=True, with_sdram=True, sdram_size=16*1024, **kwargs) - self.submodules.crg = _CRG(platform.request(platform.default_clk_name)) + clk_in = platform.request(platform.default_clk_name) + self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p) default_subtarget = SimpleSoC