From: Mike Frysinger Date: Mon, 6 Dec 2021 07:17:02 +0000 (-0500) Subject: sim: mips: migrate to standard uintXX_t types X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b331e677d748b322003d4f59eb0bd2ce3feada4b;p=binutils-gdb.git sim: mips: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides. --- diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c index e5c58ca6832..a6d1b56fdb7 100644 --- a/sim/mips/cp1.c +++ b/sim/mips/cp1.c @@ -90,8 +90,8 @@ along with this program. If not, see . */ /* Extract packed single values: */ #define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF) #define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF) -#define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \ - | (unsigned64)((l) & 0xFFFFFFFF)) +#define FP_PS_cat(u,l) (((uint64_t)((u) & (unsigned)0xFFFFFFFF) << 32) \ + | (uint64_t)((l) & 0xFFFFFFFF)) /* Explicit QNaN values. */ #define FPQNaN_SINGLE (0x7FBFFFFF) @@ -360,7 +360,7 @@ value_fcr(sim_cpu *cpu, address_word cia, int fcr) { - unsigned32 value = 0; + uint32_t value = 0; switch (fcr) { @@ -393,7 +393,7 @@ store_fcr(sim_cpu *cpu, int fcr, unsigned_word value) { - unsigned32 v; + uint32_t v; v = VL4_8(value); switch (fcr) @@ -523,8 +523,8 @@ denorm_mode(sim_cpu *cpu) /* Comparison operations. */ static sim_fpu_status -fp_test(unsigned64 op1, - unsigned64 op2, +fp_test(uint64_t op1, + uint64_t op2, FP_formats fmt, int abs, int cond, @@ -584,8 +584,8 @@ fp_test(unsigned64 op1, void fp_cmp(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt, int abs, int cond, @@ -628,11 +628,11 @@ fp_cmp(sim_cpu *cpu, /* Basic arithmetic operations. */ -static unsigned64 +static uint64_t fp_unary(sim_cpu *cpu, address_word cia, int (*sim_fpu_op)(sim_fpu *, const sim_fpu *), - unsigned64 op, + uint64_t op, FP_formats fmt) { sim_fpu wop; @@ -640,14 +640,14 @@ fp_unary(sim_cpu *cpu, sim_fpu_round round = rounding_mode (GETRM()); sim_fpu_denorm denorm = denorm_mode (cpu); sim_fpu_status status = 0; - unsigned64 result = 0; + uint64_t result = 0; /* The format type has already been checked: */ switch (fmt) { case fmt_single: { - unsigned32 res; + uint32_t res; sim_fpu_32to (&wop, op); status |= (*sim_fpu_op) (&ans, &wop); status |= sim_fpu_round_32 (&ans, round, denorm); @@ -657,7 +657,7 @@ fp_unary(sim_cpu *cpu, } case fmt_double: { - unsigned64 res; + uint64_t res; sim_fpu_64to (&wop, op); status |= (*sim_fpu_op) (&ans, &wop); status |= sim_fpu_round_64 (&ans, round, denorm); @@ -668,7 +668,7 @@ fp_unary(sim_cpu *cpu, case fmt_ps: { int status_u = 0, status_l = 0; - unsigned32 res_u, res_l; + uint32_t res_u, res_l; sim_fpu_32to (&wop, FP_PS_upper(op)); status_u |= (*sim_fpu_op) (&ans, &wop); sim_fpu_to32 (&res_u, &ans); @@ -688,12 +688,12 @@ fp_unary(sim_cpu *cpu, return result; } -static unsigned64 +static uint64_t fp_binary(sim_cpu *cpu, address_word cia, int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { sim_fpu wop1; @@ -702,14 +702,14 @@ fp_binary(sim_cpu *cpu, sim_fpu_round round = rounding_mode (GETRM()); sim_fpu_denorm denorm = denorm_mode (cpu); sim_fpu_status status = 0; - unsigned64 result = 0; + uint64_t result = 0; /* The format type has already been checked: */ switch (fmt) { case fmt_single: { - unsigned32 res; + uint32_t res; sim_fpu_32to (&wop1, op1); sim_fpu_32to (&wop2, op2); status |= (*sim_fpu_op) (&ans, &wop1, &wop2); @@ -720,7 +720,7 @@ fp_binary(sim_cpu *cpu, } case fmt_double: { - unsigned64 res; + uint64_t res; sim_fpu_64to (&wop1, op1); sim_fpu_64to (&wop2, op2); status |= (*sim_fpu_op) (&ans, &wop1, &wop2); @@ -732,7 +732,7 @@ fp_binary(sim_cpu *cpu, case fmt_ps: { int status_u = 0, status_l = 0; - unsigned32 res_u, res_l; + uint32_t res_u, res_l; sim_fpu_32to (&wop1, FP_PS_upper(op1)); sim_fpu_32to (&wop2, FP_PS_upper(op2)); status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2); @@ -757,28 +757,28 @@ fp_binary(sim_cpu *cpu, /* Common MAC code for single operands (.s or .d), defers setting FCSR. */ static sim_fpu_status inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), - unsigned64 op1, - unsigned64 op2, - unsigned64 op3, + uint64_t op1, + uint64_t op2, + uint64_t op3, int scale, int negate, FP_formats fmt, sim_fpu_round round, sim_fpu_denorm denorm, - unsigned64 *result) + uint64_t *result) { sim_fpu wop1; sim_fpu wop2; sim_fpu ans; sim_fpu_status status = 0; sim_fpu_status op_status; - unsigned64 temp = 0; + uint64_t temp = 0; switch (fmt) { case fmt_single: { - unsigned32 res; + uint32_t res; sim_fpu_32to (&wop1, op1); sim_fpu_32to (&wop2, op2); status |= sim_fpu_mul (&ans, &wop1, &wop2); @@ -804,7 +804,7 @@ inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), } case fmt_double: { - unsigned64 res; + uint64_t res; sim_fpu_64to (&wop1, op1); sim_fpu_64to (&wop2, op2); status |= sim_fpu_mul (&ans, &wop1, &wop2); @@ -842,13 +842,13 @@ inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), argument is an adjustment to the exponent of the intermediate product op1*op2. It is currently non-zero for rsqrt2 (-1), which requires an effective division by 2. */ -static unsigned64 +static uint64_t fp_mac(sim_cpu *cpu, address_word cia, int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), - unsigned64 op1, - unsigned64 op2, - unsigned64 op3, + uint64_t op1, + uint64_t op2, + uint64_t op3, int scale, int negate, FP_formats fmt) @@ -856,7 +856,7 @@ fp_mac(sim_cpu *cpu, sim_fpu_round round = rounding_mode (GETRM()); sim_fpu_denorm denorm = denorm_mode (cpu); sim_fpu_status status = 0; - unsigned64 result = 0; + uint64_t result = 0; /* The format type has already been checked: */ switch (fmt) @@ -869,7 +869,7 @@ fp_mac(sim_cpu *cpu, case fmt_ps: { int status_u, status_l; - unsigned64 result_u, result_l; + uint64_t result_u, result_l; status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2), FP_PS_upper(op3), scale, negate, fmt_single, round, denorm, &result_u); @@ -891,23 +891,23 @@ fp_mac(sim_cpu *cpu, /* Common rsqrt code for single operands (.s or .d), intermediate rounding. */ static sim_fpu_status -inner_rsqrt(unsigned64 op1, +inner_rsqrt(uint64_t op1, FP_formats fmt, sim_fpu_round round, sim_fpu_denorm denorm, - unsigned64 *result) + uint64_t *result) { sim_fpu wop1; sim_fpu ans; sim_fpu_status status = 0; sim_fpu_status op_status; - unsigned64 temp = 0; + uint64_t temp = 0; switch (fmt) { case fmt_single: { - unsigned32 res; + uint32_t res; sim_fpu_32to (&wop1, op1); status |= sim_fpu_sqrt (&ans, &wop1); status |= sim_fpu_round_32 (&ans, status, round); @@ -921,7 +921,7 @@ inner_rsqrt(unsigned64 op1, } case fmt_double: { - unsigned64 res; + uint64_t res; sim_fpu_64to (&wop1, op1); status |= sim_fpu_sqrt (&ans, &wop1); status |= sim_fpu_round_64 (&ans, round, denorm); @@ -941,16 +941,16 @@ inner_rsqrt(unsigned64 op1, return status; } -static unsigned64 +static uint64_t fp_inv_sqrt(sim_cpu *cpu, address_word cia, - unsigned64 op1, + uint64_t op1, FP_formats fmt) { sim_fpu_round round = rounding_mode (GETRM()); sim_fpu_round denorm = denorm_mode (cpu); sim_fpu_status status = 0; - unsigned64 result = 0; + uint64_t result = 0; /* The format type has already been checked: */ switch (fmt) @@ -962,7 +962,7 @@ fp_inv_sqrt(sim_cpu *cpu, case fmt_ps: { int status_u, status_l; - unsigned64 result_u, result_l; + uint64_t result_u, result_l; status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm, &result_u); status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm, @@ -981,130 +981,130 @@ fp_inv_sqrt(sim_cpu *cpu, } -unsigned64 +uint64_t fp_abs(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt); } -unsigned64 +uint64_t fp_neg(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt); } -unsigned64 +uint64_t fp_add(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt); } -unsigned64 +uint64_t fp_sub(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt); } -unsigned64 +uint64_t fp_mul(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt); } -unsigned64 +uint64_t fp_div(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt); } -unsigned64 +uint64_t fp_recip(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt); } -unsigned64 +uint64_t fp_sqrt(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt); } -unsigned64 +uint64_t fp_rsqrt(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { return fp_inv_sqrt(cpu, cia, op, fmt); } -unsigned64 +uint64_t fp_madd(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, - unsigned64 op3, + uint64_t op1, + uint64_t op2, + uint64_t op3, FP_formats fmt) { return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt); } -unsigned64 +uint64_t fp_msub(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, - unsigned64 op3, + uint64_t op1, + uint64_t op2, + uint64_t op3, FP_formats fmt) { return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt); } -unsigned64 +uint64_t fp_nmadd(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, - unsigned64 op3, + uint64_t op1, + uint64_t op2, + uint64_t op3, FP_formats fmt) { return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt); } -unsigned64 +uint64_t fp_nmsub(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, - unsigned64 op3, + uint64_t op1, + uint64_t op2, + uint64_t op3, FP_formats fmt) { return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt); @@ -1114,12 +1114,12 @@ fp_nmsub(sim_cpu *cpu, /* MIPS-3D ASE operations. */ /* Variant of fp_binary for *r.ps MIPS-3D operations. */ -static unsigned64 +static uint64_t fp_binary_r(sim_cpu *cpu, address_word cia, int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), - unsigned64 op1, - unsigned64 op2) + uint64_t op1, + uint64_t op2) { sim_fpu wop1; sim_fpu wop2; @@ -1127,8 +1127,8 @@ fp_binary_r(sim_cpu *cpu, sim_fpu_round round = rounding_mode (GETRM ()); sim_fpu_denorm denorm = denorm_mode (cpu); sim_fpu_status status_u, status_l; - unsigned64 result; - unsigned32 res_u, res_l; + uint64_t result; + uint32_t res_u, res_l; /* The format must be fmt_ps. */ status_u = 0; @@ -1149,21 +1149,21 @@ fp_binary_r(sim_cpu *cpu, return result; } -unsigned64 +uint64_t fp_add_r(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { return fp_binary_r (cpu, cia, &sim_fpu_add, op1, op2); } -unsigned64 +uint64_t fp_mul_r(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { return fp_binary_r (cpu, cia, &sim_fpu_mul, op1, op2); @@ -1221,10 +1221,10 @@ fpu_inv1_64(sim_fpu *f, const sim_fpu *l) return fpu_inv1 (f, l); } -unsigned64 +uint64_t fp_recip1(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { switch (fmt) @@ -1238,17 +1238,17 @@ fp_recip1(sim_cpu *cpu, return 0; } -unsigned64 +uint64_t fp_recip2(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { - static const unsigned64 one_single = UNSIGNED64 (0x3F800000); - static const unsigned64 one_double = UNSIGNED64 (0x3FF0000000000000); - static const unsigned64 one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000)); - unsigned64 one; + static const uint64_t one_single = UNSIGNED64 (0x3F800000); + static const uint64_t one_double = UNSIGNED64 (0x3FF0000000000000); + static const uint64_t one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000)); + uint64_t one; /* Implemented as nmsub fd, 1, fs, ft. */ switch (fmt) @@ -1319,10 +1319,10 @@ fpu_inv_sqrt1_64(sim_fpu *f, const sim_fpu *l) return fpu_inv_sqrt1 (f, l); } -unsigned64 +uint64_t fp_rsqrt1(sim_cpu *cpu, address_word cia, - unsigned64 op, + uint64_t op, FP_formats fmt) { switch (fmt) @@ -1336,17 +1336,17 @@ fp_rsqrt1(sim_cpu *cpu, return 0; } -unsigned64 +uint64_t fp_rsqrt2(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { - static const unsigned64 half_single = UNSIGNED64 (0x3F000000); - static const unsigned64 half_double = UNSIGNED64 (0x3FE0000000000000); - static const unsigned64 half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000)); - unsigned64 half; + static const uint64_t half_single = UNSIGNED64 (0x3F000000); + static const uint64_t half_double = UNSIGNED64 (0x3FE0000000000000); + static const uint64_t half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000)); + uint64_t half; /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is done by scaling the exponent during multiply. */ @@ -1374,8 +1374,8 @@ convert (sim_cpu *cpu, sim_fpu wop; sim_fpu_round round = rounding_mode (rm); sim_fpu_denorm denorm = denorm_mode (cpu); - unsigned32 result32; - unsigned64 result64; + uint32_t result32; + uint64_t result64; sim_fpu_status status = 0; /* Convert the input to sim_fpu internal format */ @@ -1438,30 +1438,30 @@ convert (sim_cpu *cpu, return result64; } -unsigned64 +uint64_t ps_lower(sim_cpu *cpu, address_word cia, - unsigned64 op) + uint64_t op) { return FP_PS_lower (op); } -unsigned64 +uint64_t ps_upper(sim_cpu *cpu, address_word cia, - unsigned64 op) + uint64_t op) { return FP_PS_upper(op); } -unsigned64 +uint64_t pack_ps(sim_cpu *cpu, address_word cia, - unsigned64 op1, - unsigned64 op2, + uint64_t op1, + uint64_t op2, FP_formats fmt) { - unsigned64 result = 0; + uint64_t result = 0; /* The registers must specify FPRs valid for operands of type "fmt". If they are not valid, the result is undefined. */ @@ -1472,7 +1472,7 @@ pack_ps(sim_cpu *cpu, case fmt_single: { sim_fpu wop; - unsigned32 res_u, res_l; + uint32_t res_u, res_l; sim_fpu_32to (&wop, op1); sim_fpu_to32 (&res_u, &wop); sim_fpu_32to (&wop, op2); @@ -1488,19 +1488,19 @@ pack_ps(sim_cpu *cpu, return result; } -unsigned64 +uint64_t convert_ps (sim_cpu *cpu, address_word cia, int rm, - unsigned64 op, + uint64_t op, FP_formats from, FP_formats to) { sim_fpu wop_u, wop_l; sim_fpu_round round = rounding_mode (rm); sim_fpu_denorm denorm = denorm_mode (cpu); - unsigned32 res_u, res_l; - unsigned64 result; + uint32_t res_u, res_l; + uint64_t result; sim_fpu_status status_u = 0, status_l = 0; /* As convert, but used only for paired values (formats PS, PW) */ @@ -1527,7 +1527,7 @@ convert_ps (sim_cpu *cpu, case fmt_word: /* fmt_pw */ status_u |= sim_fpu_to32u (&res_u, &wop_u, round); status_l |= sim_fpu_to32u (&res_l, &wop_l, round); - result = (((unsigned64)res_u) << 32) | (unsigned64)res_l; + result = (((uint64_t)res_u) << 32) | (uint64_t)res_l; break; case fmt_ps: status_u |= sim_fpu_round_32 (&wop_u, 0, round); diff --git a/sim/mips/dsp.igen b/sim/mips/dsp.igen index bc103e44896..ec11011042a 100644 --- a/sim/mips/dsp.igen +++ b/sim/mips/dsp.igen @@ -25,22 +25,22 @@ :function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat { int i; - signed32 h0 = 0; - signed16 h1, h2; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 result = 0; + int32_t h0 = 0; + int16_t h1, h2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); if (op == 0) // ADD - h0 = (signed32)h1 + (signed32)h2; + h0 = (int32_t)h1 + (int32_t)h2; else if (op == 1) // SUB - h0 = (signed32)h1 - (signed32)h2; + h0 = (int32_t)h1 - (int32_t)h2; else // MUL - h0 = (signed32)h1 * (signed32)h2; - if (h0 > (signed32)0x7fff || h0 < (signed32)0xffff8000) + h0 = (int32_t)h1 * (int32_t)h2; + if (h0 > (int32_t)0x7fff || h0 < (int32_t)0xffff8000) { if (op == 0 || op == 1) // ADD, SUB DSPCR |= DSPCR_OUFLAG4; @@ -48,13 +48,13 @@ DSPCR |= DSPCR_OUFLAG5; if (sat == 1) { - if (h0 > (signed32)0x7fff) + if (h0 > (int32_t)0x7fff) h0 = 0x7fff; else h0 = 0x8000; } } - result |= ((unsigned32)((unsigned16)h0) << i); + result |= ((uint32_t)((uint16_t)h0) << i); } GPR[rd] = EXTEND32 (result); } @@ -62,17 +62,17 @@ // op: 0 = ADD, 1 = SUB :function:::void:do_w_op:int rd, int rs, int rt, int op { - signed64 h0; - signed32 h1, h2; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 result = 0; - h1 = (signed32)v1; - h2 = (signed32)v2; + int64_t h0; + int32_t h1, h2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t result = 0; + h1 = (int32_t)v1; + h2 = (int32_t)v2; if (op == 0) // ADD - h0 = (signed64)h1 + (signed64)h2; + h0 = (int64_t)h1 + (int64_t)h2; else // SUB - h0 = (signed64)h1 - (signed64)h2; + h0 = (int64_t)h1 - (int64_t)h2; if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000)) { DSPCR |= DSPCR_OUFLAG4; @@ -89,19 +89,19 @@ :function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat { int i; - unsigned32 h0; - unsigned8 h1, h2; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 result = 0; + uint32_t h0; + uint8_t h1, h2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); if (op == 0) // ADD - h0 = (unsigned32)h1 + (unsigned32)h2; + h0 = (uint32_t)h1 + (uint32_t)h2; else // SUB - h0 = (unsigned32)h1 - (unsigned32)h2; + h0 = (uint32_t)h1 - (uint32_t)h2; if (h0 & 0x100) { DSPCR |= DSPCR_OUFLAG4; @@ -113,7 +113,7 @@ h0 = 0; } } - result |= ((unsigned32)((unsigned8)h0) << i); + result |= ((uint32_t)((uint8_t)h0) << i); } GPR[rd] = EXTEND32 (result); } @@ -122,12 +122,12 @@ :function:::void:do_qb_shift:int rd, int rt, int shift, int op { int i, j; - unsigned8 h0; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + uint8_t h0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 8, v1 >>= 8) { - h0 = (unsigned8)(v1 & 0xff); + h0 = (uint8_t)(v1 & 0xff); if (op == 0) // left { for (j = 7; j >= 8 - shift; j--) @@ -142,7 +142,7 @@ } else // right h0 = h0 >> shift; - result |= ((unsigned32)h0 << i); + result |= ((uint32_t)h0 << i); } GPR[rd] = EXTEND32 (result); } @@ -152,13 +152,13 @@ :function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat { int i, j; - signed16 h0; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + int16_t h0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; int setcond; for (i = 0; i < 32; i += 16, v1 >>= 16) { - h0 = (signed16)(v1 & 0xffff); + h0 = (int16_t)(v1 & 0xffff); if (op == 0) // left { setcond = 0; @@ -203,7 +203,7 @@ h0 = h0 >> shift; } - result |= ((unsigned32)((unsigned16)h0) << i); + result |= ((uint32_t)((uint16_t)h0) << i); } GPR[rd] = EXTEND32 (result); } @@ -211,8 +211,8 @@ :function:::void:do_w_shll:int rd, int rt, int shift { int i; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; int setcond = 0; if (v1 & (1 << 31)) { @@ -250,29 +250,29 @@ :function:::void:do_ph_s_absq:int rd, int rt { int i; - signed16 h0; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + int16_t h0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 16, v1 >>= 16) { - h0 = (signed16)(v1 & 0xffff); - if (h0 == (signed16)0x8000) + h0 = (int16_t)(v1 & 0xffff); + if (h0 == (int16_t)0x8000) { DSPCR |= DSPCR_OUFLAG4; h0 = 0x7fff; } else if (h0 & 0x8000) h0 = -h0; - result |= ((unsigned32)((unsigned16)h0) << i); + result |= ((uint32_t)((uint16_t)h0) << i); } GPR[rd] = EXTEND32 (result); } :function:::void:do_w_s_absq:int rd, int rt { - unsigned32 v1 = GPR[rt]; - signed32 h0 = (signed32)v1; - if (h0 == (signed32)0x80000000) + uint32_t v1 = GPR[rt]; + int32_t h0 = (int32_t)v1; + if (h0 == (int32_t)0x80000000) { DSPCR |= DSPCR_OUFLAG4; h0 = 0x7fffffff; @@ -285,30 +285,30 @@ :function:::void:do_qb_s_absq:int rd, int rt { int i; - signed8 q0; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + int8_t q0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 8, v1 >>= 8) { - q0 = (signed8)(v1 & 0xff); - if (q0 == (signed8)0x80) + q0 = (int8_t)(v1 & 0xff); + if (q0 == (int8_t)0x80) { DSPCR |= DSPCR_OUFLAG4; q0 = 0x7f; } else if (q0 & 0x80) q0 = -q0; - result |= ((unsigned32)((unsigned8)q0) << i); + result |= ((uint32_t)((uint8_t)q0) << i); } GPR[rd] = EXTEND32 (result); } :function:::void:do_addsc:int rd, int rs, int rt { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned64 h0; - h0 = (unsigned64)v1 + (unsigned64)v2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint64_t h0; + h0 = (uint64_t)v1 + (uint64_t)v2; if (h0 & 0x100000000LL) DSPCR |= DSPCR_CARRY; GPR[rd] = EXTEND32 (h0); @@ -316,13 +316,13 @@ :function:::void:do_addwc:int rd, int rs, int rt { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned64 h0; - signed32 h1 = (signed32) v1; - signed32 h2 = (signed32) v2; - h0 = (signed64)h1 + (signed64)h2 - + (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint64_t h0; + int32_t h1 = (int32_t) v1; + int32_t h2 = (int32_t) v2; + h0 = (int64_t)h1 + (int64_t)h2 + + (int64_t)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK); if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000)) DSPCR |= DSPCR_OUFLAG4; GPR[rd] = EXTEND32 (h0); @@ -331,8 +331,8 @@ :function:::void:do_bitrev:int rd, int rt { int i; - unsigned32 v1 = GPR[rt]; - unsigned32 h1 = 0; + uint32_t v1 = GPR[rt]; + uint32_t h1 = 0; for (i = 0; i < 16; i++) { if (v1 & (1 << i)) @@ -344,30 +344,30 @@ // op: 0 = EXTPV, 1 = EXTPDPV :function:::void:do_extpv:int rt, int ac, int rs, int op { - unsigned32 size = GPR[rs] & 0x1f; + uint32_t size = GPR[rs] & 0x1f; do_extp (SD_, rt, ac, size, op); } // op: 0 = EXTRV, 1 = EXTRV_R, 2 = EXTRV_RS :function:::void:do_extrv:int rt, int ac, int rs, int op { - unsigned32 shift = GPR[rs] & 0x1f; + uint32_t shift = GPR[rs] & 0x1f; do_w_extr (SD_, rt, ac, shift, op); } :function:::void:do_extrv_s_h:int rt, int ac, int rs { - unsigned32 shift = GPR[rs] & 0x1f; + uint32_t shift = GPR[rs] & 0x1f; do_h_extr (SD_, rt, ac, shift); } :function:::void:do_insv:int rt, int rs { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; - unsigned32 size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK; - unsigned32 mask1, mask2, mask3, result; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + uint32_t size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK; + uint32_t mask1, mask2, mask3, result; if (size < 32) mask1 = (1 << size) - 1; else @@ -394,11 +394,11 @@ :function:::void:do_modsub:int rd, int rs, int rt { - unsigned32 result = 0; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 decr = v2 & 0xff; - unsigned32 lastindex = (v2 & 0xffff00) >> 8; + uint32_t result = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t decr = v2 & 0xff; + uint32_t lastindex = (v2 & 0xffff00) >> 8; if (v1 == 0) result = lastindex; else @@ -408,7 +408,7 @@ :function:::void:do_mthlip:int rs, int ac { - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; DSPHI(ac) = DSPLO(ac); DSPLO(ac) = GPR[rs]; if (pos >= 32) @@ -422,29 +422,29 @@ :function:::void:do_mulsaq_s_w_ph:int ac, int rs, int rt { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); - result = (signed32) 0x7fffffff; + result = (int32_t) 0x7fffffff; } else - result = ((signed32)h1 * (signed32)h2) << 1; + result = ((int32_t)h1 * (int32_t)h2) << 1; if (i == 0) - prod -= (signed64) result; + prod -= (int64_t) result; else - prod += (signed64) result; + prod += (int64_t) result; } DSPLO(ac) = EXTEND32 (prod); DSPHI(ac) = EXTEND32 (prod >> 32); @@ -453,26 +453,26 @@ :function:::void:do_ph_packrl:int rd, int rs, int rt { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; GPR[rd] = EXTEND32 ((v1 << 16) + (v2 >> 16)); } :function:::void:do_qb_pick:int rd, int rs, int rt { int i, j; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned8 h1, h2; - unsigned32 result = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint8_t h1, h2; + uint32_t result = 0; for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j))) - result |= (unsigned32)(h1 << i); + result |= (uint32_t)(h1 << i); else - result |= (unsigned32)(h2 << i); + result |= (uint32_t)(h2 << i); } GPR[rd] = EXTEND32 (result); } @@ -480,18 +480,18 @@ :function:::void:do_ph_pick:int rd, int rs, int rt { int i, j; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned16 h1, h2; - unsigned32 result = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint16_t h1, h2; + uint32_t result = 0; for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16) { - h1 = (unsigned16)(v1 & 0xffff); - h2 = (unsigned16)(v2 & 0xffff); + h1 = (uint16_t)(v1 & 0xffff); + h2 = (uint16_t)(v2 & 0xffff); if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j))) - result |= (unsigned32)(h1 << i); + result |= (uint32_t)(h1 << i); else - result |= (unsigned32)(h2 << i); + result |= (uint32_t)(h2 << i); } GPR[rd] = EXTEND32 (result); } @@ -499,7 +499,7 @@ // op: 0 = QBR, 1 = QBRA, 2 = QBL, 3 = QBLA :function:::void:do_qb_ph_precequ:int rd, int rt, int op { - unsigned32 v1 = GPR[rt]; + uint32_t v1 = GPR[rt]; if (op == 0) GPR[rd] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7); else if (op == 1) @@ -513,7 +513,7 @@ // op: 0 = QBR, 1 = QBRA, 2 = QBL, 3 = QBLA :function:::void:do_qb_ph_preceu:int rd, int rt, int op { - unsigned32 v1 = GPR[rt]; + uint32_t v1 = GPR[rt]; if (op == 0) GPR[rd] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff); else if (op == 1) @@ -527,7 +527,7 @@ // op: 0 = .PHL, 1 = PHR :function:::void:do_w_preceq:int rd, int rt, int op { - unsigned32 v1 = GPR[rt]; + uint32_t v1 = GPR[rt]; if (op == 0) GPR[rd] = EXTEND32 (v1 & 0xffff0000); else if (op == 1) @@ -536,19 +536,19 @@ :function:::void:do_w_ph_precrq:int rd, int rs, int rt { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 tempu = (v1 & 0xffff0000) >> 16; - unsigned32 tempv = (v2 & 0xffff0000) >> 16; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t tempu = (v1 & 0xffff0000) >> 16; + uint32_t tempv = (v2 & 0xffff0000) >> 16; GPR[rd] = EXTEND32 ((tempu << 16) | tempv); } // sat: 0 = PRECRQ.QB.PH, 1 = PRECRQU_S.QB.PH :function:::void:do_ph_qb_precrq:int rd, int rs, int rt, int sat { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 tempu = 0, tempv = 0, tempw = 0, tempx = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t tempu = 0, tempv = 0, tempw = 0, tempx = 0; if (sat == 0) { tempu = (v1 & 0xff000000) >> 24; @@ -563,7 +563,7 @@ DSPCR |= DSPCR_OUFLAG6; tempu = 0; } - else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80)) + else if (!(v1 & 0x80000000) && ((v1 >> 16) > (uint32_t)0x7f80)) { DSPCR |= DSPCR_OUFLAG6; tempu = 0xff; @@ -575,7 +575,7 @@ DSPCR |= DSPCR_OUFLAG6; tempv = 0; } - else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80)) + else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (uint32_t)0x7f80)) { DSPCR |= DSPCR_OUFLAG6; tempv = 0xff; @@ -587,7 +587,7 @@ DSPCR |= DSPCR_OUFLAG6; tempw = 0; } - else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80)) + else if (!(v2 & 0x80000000) && ((v2 >> 16) > (uint32_t)0x7f80)) { DSPCR |= DSPCR_OUFLAG6; tempw = 0xff; @@ -599,7 +599,7 @@ DSPCR |= DSPCR_OUFLAG6; tempx = 0; } - else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80)) + else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (uint32_t)0x7f80)) { DSPCR |= DSPCR_OUFLAG6; tempx = 0xff; @@ -612,48 +612,48 @@ :function:::void:do_w_ph_rs_precrq:int rd, int rs, int rt { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed32 h1 = (signed32)v1; - signed32 h2 = (signed32)v2; - signed64 temp1 = (signed64)h1 + (signed64)0x8000; - signed32 temp2; - signed64 temp3 = (signed64)h2 + (signed64)0x8000; - signed32 temp4; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int32_t h1 = (int32_t)v1; + int32_t h2 = (int32_t)v2; + int64_t temp1 = (int64_t)h1 + (int64_t)0x8000; + int32_t temp2; + int64_t temp3 = (int64_t)h2 + (int64_t)0x8000; + int32_t temp4; if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000)) { DSPCR |= DSPCR_OUFLAG6; temp2 = 0x7fff; } else - temp2 = (signed32)((temp1 & 0xffff0000) >> 16); + temp2 = (int32_t)((temp1 & 0xffff0000) >> 16); if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000)) { DSPCR |= DSPCR_OUFLAG6; temp4 = 0x7fff; } else - temp4 = (signed32)((temp3 & 0xffff0000) >> 16); + temp4 = (int32_t)((temp3 & 0xffff0000) >> 16); GPR[rd] = EXTEND32 ((temp2 << 16) | temp4); } :function:::void:do_qb_w_raddu:int rd, int rs { int i; - unsigned8 h0; - unsigned32 v1 = GPR[rs]; - unsigned32 result = 0; + uint8_t h0; + uint32_t v1 = GPR[rs]; + uint32_t result = 0; for (i = 0; i < 32; i += 8, v1 >>= 8) { - h0 = (unsigned8)(v1 & 0xff); - result += (unsigned32)h0; + h0 = (uint8_t)(v1 & 0xff); + result += (uint32_t)h0; } GPR[rd] = EXTEND32 (result); } :function:::void:do_rddsp:int rd, int mask { - unsigned32 result = 0; + uint32_t result = 0; if (mask & 0x1) { result &= (~DSPCR_POS_SMASK); @@ -694,19 +694,19 @@ GPR[rd] = EXTEND32 ((p2 << 24) | (p2 << 16) | (p2 << 8) | p2); else if (op == 1) { - unsigned32 v1 = GPR[p2] & 0xff; + uint32_t v1 = GPR[p2] & 0xff; GPR[rd] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1); } else if (op == 2) { - signed32 v1 = p2; + int32_t v1 = p2; if (v1 & 0x200) v1 |= 0xfffffc00; GPR[rd] = EXTEND32 ((v1 << 16) | (v1 & 0xffff)); } else if (op == 3) { - unsigned32 v1 = GPR[p2]; + uint32_t v1 = GPR[p2]; v1 = v1 & 0xffff; GPR[rd] = EXTEND32 ((v1 << 16) | v1); } @@ -714,7 +714,7 @@ :function:::void:do_shilov:int ac, int rs { - signed32 shift = GPR[rs] & 0x3f; + int32_t shift = GPR[rs] & 0x3f; do_shilo (SD_, ac, shift); } @@ -722,38 +722,38 @@ // sat: 0 = normal, 1 = saturate/rounding :function:::void:do_ph_shl:int rd, int rt, int rs, int op, int sat { - unsigned32 shift = GPR[rs] & 0xf; + uint32_t shift = GPR[rs] & 0xf; do_ph_shift (SD_, rd, rt, shift, op, sat); } // op: 0 = SHLLV, 1 = SHRLV :function:::void:do_qb_shl:int rd, int rt, int rs, int op { - unsigned32 shift = GPR[rs] & 0x7; + uint32_t shift = GPR[rs] & 0x7; do_qb_shift (SD_, rd, rt, shift, op); } :function:::void:do_w_s_shllv:int rd, int rt, int rs { - unsigned32 shift = GPR[rs] & 0x1f; + uint32_t shift = GPR[rs] & 0x1f; do_w_shll (SD_, rd, rt, shift); } :function:::void:do_ph_shrlv:int rd, int rt, int rs { - unsigned32 shift = GPR[rs] & 0xf; + uint32_t shift = GPR[rs] & 0xf; do_ph_shrl (SD_, rd, rt, shift); } :function:::void:do_w_r_shrav:int rd, int rt, int rs { - unsigned32 shift = GPR[rs] & 0x1f; + uint32_t shift = GPR[rs] & 0x1f; do_w_shra (SD_, rd, rt, shift); } :function:::void:do_wrdsp:int rs, int mask { - unsigned32 v1 = GPR[rs]; + uint32_t v1 = GPR[rs]; if (mask & 0x1) { DSPCR &= (~DSPCR_POS_SMASK); @@ -789,25 +789,25 @@ // round: 0 = no rounding, 1 = rounding :function:::void:do_qb_shrav:int rd, int rt, int rs, int round { - unsigned32 shift = GPR[rs] & 0x7; + uint32_t shift = GPR[rs] & 0x7; do_qb_shra (SD_, rd, rt, shift, round); } :function:::void:do_append:int rt, int rs, int sa { - unsigned32 v0 = GPR[rs]; - unsigned32 v1 = GPR[rt]; - unsigned32 result; - unsigned32 mask = (1 << sa) - 1; + uint32_t v0 = GPR[rs]; + uint32_t v1 = GPR[rt]; + uint32_t result; + uint32_t mask = (1 << sa) - 1; result = (v1 << sa) | (v0 & mask); GPR[rt] = EXTEND32 (result); } :function:::void:do_balign:int rt, int rs, int bp { - unsigned32 v0 = GPR[rs]; - unsigned32 v1 = GPR[rt]; - unsigned32 result; + uint32_t v0 = GPR[rs]; + uint32_t v1 = GPR[rt]; + uint32_t result; if (bp == 0) result = v1; else @@ -818,23 +818,23 @@ :function:::void:do_ph_w_mulsa:int ac, int rs, int rt { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); - result = (signed32)h1 * (signed32)h2; + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); + result = (int32_t)h1 * (int32_t)h2; if (i == 0) - prod -= (signed64) result; + prod -= (int64_t) result; else - prod += (signed64) result; + prod += (int64_t) result; } DSPLO(ac) = EXTEND32 (prod); DSPHI(ac) = EXTEND32 (prod >> 32); @@ -842,20 +842,20 @@ :function:::void:do_ph_qb_precr:int rd, int rs, int rt { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 tempu = (v1 & 0xff0000) >> 16; - unsigned32 tempv = (v1 & 0xff); - unsigned32 tempw = (v2 & 0xff0000) >> 16; - unsigned32 tempx = (v2 & 0xff); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t tempu = (v1 & 0xff0000) >> 16; + uint32_t tempv = (v1 & 0xff); + uint32_t tempw = (v2 & 0xff0000) >> 16; + uint32_t tempx = (v2 & 0xff); GPR[rd] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx); } :function:::void:do_prepend:int rt, int rs, int sa { - unsigned32 v0 = GPR[rs]; - unsigned32 v1 = GPR[rt]; - unsigned32 result; + uint32_t v0 = GPR[rs]; + uint32_t v1 = GPR[rt]; + uint32_t result; if (sa == 0) result = v1; else @@ -865,8 +865,8 @@ :function:::void:do_w_shra:int rd, int rt, int shift { - unsigned32 result = GPR[rt]; - signed32 h0 = (signed32)result; + uint32_t result = GPR[rt]; + int32_t h0 = (int32_t)result; if (shift != 0 && (h0 & (1 << (shift-1)))) h0 = (h0 >> shift) + 1; else @@ -1200,24 +1200,24 @@ :function:::void:do_qb_muleu:int rd, int rs, int rt, int loc { int i; - unsigned32 result = 0; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned16 h1, h2; - unsigned32 prod; + uint32_t result = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint16_t h1, h2; + uint32_t prod; if (loc == 0) v1 >>= 16; for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16) { - h1 = (unsigned16)(v1 & 0xff); - h2 = (unsigned16)(v2 & 0xffff); - prod = (unsigned32)h1 * (unsigned32)h2; + h1 = (uint16_t)(v1 & 0xff); + h2 = (uint16_t)(v2 & 0xffff); + prod = (uint32_t)h1 * (uint32_t)h2; if (prod > 0xffff) { DSPCR |= DSPCR_OUFLAG5; prod = 0xffff; } - result |= ((unsigned32)prod << i); + result |= ((uint32_t)prod << i); } GPR[rd] = EXTEND32 (result); } @@ -1240,27 +1240,27 @@ :function:::void:do_ph_mulq:int rd, int rs, int rt, int round { int i; - unsigned32 result = 0; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 prod; + uint32_t result = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t prod; for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) { DSPCR |= DSPCR_OUFLAG5; prod = 0x7fffffff; } else { - prod = ((signed32)h1 * (signed32)h2) << 1; + prod = ((int32_t)h1 * (int32_t)h2) << 1; if (round == 1) - prod += (signed32)0x8000; + prod += (int32_t)0x8000; } - result |= (((unsigned32)prod >> 16) << i); + result |= (((uint32_t)prod >> 16) << i); } GPR[rd] = EXTEND32 (result); } @@ -1275,27 +1275,27 @@ // loc: 0 = phl, 1 = phr :function:::void:do_ph_muleq:int rd, int rs, int rt, int loc { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 prod; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t prod; if (loc == 0) { - h1 = (signed16)(v1 >> 16); - h2 = (signed16)(v2 >> 16); + h1 = (int16_t)(v1 >> 16); + h2 = (int16_t)(v2 >> 16); } else { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); } - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) { DSPCR |= DSPCR_OUFLAG5; prod = 0x7fffffff; } else - prod = ((signed32)h1 * (signed32)h2) << 1; + prod = ((int32_t)h1 * (int32_t)h2) << 1; GPR[rd] = EXTEND32 (prod); } @@ -1318,12 +1318,12 @@ :function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned8 h1, h2; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint8_t h1, h2; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; if (loc == 0) { v1 >>= 16; @@ -1331,12 +1331,12 @@ } for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); if (op == 0) // DPAU - prod += (unsigned64)h1 * (unsigned64)h2; + prod += (uint64_t)h1 * (uint64_t)h2; else // DPSU - prod -= (unsigned64)h1 * (unsigned64)h2; + prod -= (uint64_t)h1 * (uint64_t)h2; } DSPLO(ac) = EXTEND32 (prod); DSPHI(ac) = EXTEND32 (prod >> 32); @@ -1374,29 +1374,29 @@ :function:::void:do_ph_dot_product:int ac, int rs, int rt, int op { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); - result = (signed32)0x7fffffff; + result = (int32_t)0x7fffffff; } else - result = ((signed32)h1 * (signed32)h2) << 1; + result = ((int32_t)h1 * (int32_t)h2) << 1; if (op == 0) // DPAQ - prod += (signed64)result; + prod += (int64_t)result; else // DPSQ - prod -= (signed64)result; + prod -= (int64_t)result; } DSPLO(ac) = EXTEND32 (prod); DSPHI(ac) = EXTEND32 (prod >> 32); @@ -1426,41 +1426,41 @@ // op: 0 = DPAQ 1 = DPSQ :function:::void:do_w_dot_product:int ac, int rs, int rt, int op { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed32 h1, h2; - signed64 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - unsigned32 resultlo; - unsigned32 resulthi; - unsigned32 carry; - unsigned64 temp1; - signed64 temp2; - h1 = (signed32) v1; - h2 = (signed32) v2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int32_t h1, h2; + int64_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + uint32_t resultlo; + uint32_t resulthi; + uint32_t carry; + uint64_t temp1; + int64_t temp2; + h1 = (int32_t) v1; + h2 = (int32_t) v2; if (h1 == 0x80000000 && h2 == 0x80000000) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); - result = (signed64) 0x7fffffffffffffffLL; + result = (int64_t) 0x7fffffffffffffffLL; } else - result = ((signed64)h1 * (signed64)h2) << 1; - resultlo = (unsigned32)(result); - resulthi = (unsigned32)(result >> 32); + result = ((int64_t)h1 * (int64_t)h2) << 1; + resultlo = (uint32_t)(result); + resulthi = (uint32_t)(result >> 32); if (op ==0) // DPAQ { - temp1 = (unsigned64)lo + (unsigned64)resultlo; - carry = (unsigned32)((temp1 >> 32) & 1); - temp2 = (signed64)((signed32)hi) + (signed64)((signed32)resulthi) + - (signed64)((signed32)carry); + temp1 = (uint64_t)lo + (uint64_t)resultlo; + carry = (uint32_t)((temp1 >> 32) & 1); + temp2 = (int64_t)((int32_t)hi) + (int64_t)((int32_t)resulthi) + + (int64_t)((int32_t)carry); } else // DPSQ { - temp1 = (unsigned64)lo - (unsigned64)resultlo; - carry = (unsigned32)((temp1 >> 32) & 1); - temp2 = (signed64)((signed32)hi) - (signed64)((signed32)resulthi) - - (signed64)((signed32)carry); + temp1 = (uint64_t)lo - (uint64_t)resultlo; + carry = (uint32_t)((temp1 >> 32) & 1); + temp2 = (int64_t)((int32_t)hi) - (int64_t)((int32_t)resulthi) - + (int64_t)((int32_t)carry); } if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL)) { @@ -1502,38 +1502,38 @@ :function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); if (loc == 0) { - h1 = (signed16)(v1 >> 16); - h2 = (signed16)(v2 >> 16); + h1 = (int16_t)(v1 >> 16); + h2 = (int16_t)(v2 >> 16); } else { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); } - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); - result = (signed32)0x7fffffff; + result = (int32_t)0x7fffffff; } else - result = ((signed32)h1 * (signed32)h2) << 1; - prod += (signed64)result; + result = ((int32_t)h1 * (int32_t)h2) << 1; + prod += (int64_t)result; if (op == 1) // MAQ_SA { if (prod & 0x8000000000000000LL) { for (i = 62; i >= 31; i--) { - if (!(prod & ((signed64)1 << i))) + if (!(prod & ((int64_t)1 << i))) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); prod = 0xffffffff80000000LL; @@ -1545,7 +1545,7 @@ { for (i = 62; i >= 31; i--) { - if (prod & ((signed64)1 << i)) + if (prod & ((int64_t)1 << i)) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); prod = 0x7fffffff; @@ -1632,14 +1632,14 @@ :function:::void:do_qb_cmpu:int rs, int rt, int op { int i, j; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned8 h1, h2; - unsigned32 mask; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint8_t h1, h2; + uint32_t mask; for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); DSPCR &= mask; if (op == 0) // EQ @@ -1676,14 +1676,14 @@ :function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op { int i, j; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned8 h1, h2; - unsigned32 result = 0; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint8_t h1, h2; + uint32_t result = 0; for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); if (op == 0) // EQ result |= ((h1 == h2) << j); else if (op == 1) // LT @@ -1719,14 +1719,14 @@ :function:::void:do_ph_cmpu:int rs, int rt, int op { int i, j; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - unsigned32 mask; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + uint32_t mask; for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); DSPCR &= mask; if (op == 0) // EQ @@ -1784,16 +1784,16 @@ :function:::void:do_w_extr:int rt, int ac, int shift, int op { int i; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; - signed64 result = (signed64)prod; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; + int64_t result = (int64_t)prod; int setcond = 0; if (!(prod & 0x8000000000000000LL)) { for (i = 62; i >= (shift + 31); i--) { - if (prod & ((unsigned64)1 << i)) + if (prod & ((uint64_t)1 << i)) { DSPCR |= DSPCR_OUFLAG7; setcond = 1; @@ -1810,7 +1810,7 @@ { for (i = 62; i >= (shift + 31); i--) { - if (!(prod & ((unsigned64)1 << i))) + if (!(prod & ((uint64_t)1 << i))) { DSPCR |= DSPCR_OUFLAG7; setcond = 2; @@ -1889,11 +1889,11 @@ :function:::void:do_h_extr:int rt, int ac, int shift { int i; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; - signed64 result = (signed64)prod; - signed64 value = 0xffffffffffff8000LL; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; + int64_t result = (int64_t)prod; + int64_t value = 0xffffffffffff8000LL; result >>= shift; if (result > 0x7fff) { @@ -1925,15 +1925,15 @@ // op: 0 = EXTP, 1 = EXTPDP :function:::void:do_extp:int rt, int ac, int size, int op { - signed32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; - unsigned64 result = 0; + int32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; + uint64_t result = 0; if (pos - (size + 1) >= -1) { prod >>= (pos - size); - result = prod & (((unsigned64)1 << (size + 1)) - 1); + result = prod & (((uint64_t)1 << (size + 1)) - 1); DSPCR &= (~DSPCR_EFI_SMASK); if (op == 1) // EXTPDP { @@ -1986,9 +1986,9 @@ :function:::void:do_shilo:int ac, int shift { - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; if (shift > 31) shift = shift - 64; if (shift >= 0) @@ -2061,7 +2061,7 @@ "bposge32 " *dsp: { - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; address_word offset = EXTEND16 (OFFSET) << 2; if (pos >= 32) { diff --git a/sim/mips/dsp2.igen b/sim/mips/dsp2.igen index 299eb2f001f..032ef1e043f 100644 --- a/sim/mips/dsp2.igen +++ b/sim/mips/dsp2.igen @@ -26,20 +26,20 @@ :function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat { int i; - unsigned32 h0; - unsigned16 h1, h2; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 result = 0; + uint32_t h0; + uint16_t h1, h2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (unsigned16)(v1 & 0xffff); - h2 = (unsigned16)(v2 & 0xffff); + h1 = (uint16_t)(v1 & 0xffff); + h2 = (uint16_t)(v2 & 0xffff); if (op == 0) // ADD - h0 = (unsigned32)h1 + (unsigned32)h2; + h0 = (uint32_t)h1 + (uint32_t)h2; else // SUB - h0 = (unsigned32)h1 - (unsigned32)h2; - if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT + h0 = (uint32_t)h1 - (uint32_t)h2; + if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT { DSPCR |= DSPCR_OUFLAG4; if (sat == 1) @@ -51,7 +51,7 @@ if (sat == 1) h0 = 0x0; } - result |= ((unsigned32)((unsigned16)h0) << i); + result |= ((uint32_t)((uint16_t)h0) << i); } GPR[rd] = EXTEND32 (result); } @@ -61,24 +61,24 @@ :function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round { int i; - unsigned32 h0; - unsigned8 h1, h2; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 result = 0; + uint32_t h0; + uint8_t h1, h2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); if (op == 0) // ADD - h0 = (unsigned32)h1 + (unsigned32)h2; + h0 = (uint32_t)h1 + (uint32_t)h2; else // SUB - h0 = (unsigned32)h1 - (unsigned32)h2; + h0 = (uint32_t)h1 - (uint32_t)h2; if (round == 1) h0 = (h0 + 1) >> 1; else h0 = h0 >> 1; - result |= ((unsigned32)((unsigned8)h0) << i); + result |= ((uint32_t)((uint8_t)h0) << i); } GPR[rd] = EXTEND32 (result); } @@ -87,15 +87,15 @@ :function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op { int i, j; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned8 h1, h2; - unsigned32 result = 0; - unsigned32 mask; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint8_t h1, h2; + uint32_t result = 0; + uint32_t mask; for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) { - h1 = (unsigned8)(v1 & 0xff); - h2 = (unsigned8)(v2 & 0xff); + h1 = (uint8_t)(v1 & 0xff); + h2 = (uint8_t)(v2 & 0xff); mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); DSPCR &= mask; if (op == 0) // EQ @@ -121,22 +121,22 @@ :function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); - result = (signed32)h1 * (signed32)h2; + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); + result = (int32_t)h1 * (int32_t)h2; if (op == 0) // DPA - prod += (signed64)result; + prod += (int64_t)result; else // DPS - prod -= (signed64)result; + prod -= (int64_t)result; } DSPLO(ac) = EXTEND32 (prod); DSPHI(ac) = EXTEND32 (prod >> 32); @@ -145,37 +145,37 @@ // round: 0 = no rounding, 1 = rounding :function:::void:do_w_mulq:int rd, int rs, int rt, int round { - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed32 w1, w2; - signed64 prod; - unsigned32 result; - w1 = (signed32) v1; - w2 = (signed32) v2; - if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000) + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int32_t w1, w2; + int64_t prod; + uint32_t result; + w1 = (int32_t) v1; + w2 = (int32_t) v2; + if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000) { DSPCR |= DSPCR_OUFLAG5; prod = 0x7fffffff; } else { - prod = ((signed64) w1 * (signed64) w2) << 1; + prod = ((int64_t) w1 * (int64_t) w2) << 1; if (round == 1) prod += 0x0000000080000000LL; prod = prod >> 32; } - result = (unsigned32) prod; + result = (uint32_t) prod; GPR[rd] = EXTEND32 (result); } // round: 0 = no rounding, 1 = rounding :function:::void:do_precr_sra:int rt, int rs, int sa, int round { - unsigned32 v1 = GPR[rt]; - unsigned32 v2 = GPR[rs]; - signed32 w1 = (signed32) v1; - signed32 w2 = (signed32) v2; - signed32 result; + uint32_t v1 = GPR[rt]; + uint32_t v2 = GPR[rs]; + int32_t w1 = (int32_t) v1; + int32_t w2 = (int32_t) v2; + int32_t result; if (sa != 0) { if (round == 1 && (w1 & (1 << (sa - 1)))) @@ -196,12 +196,12 @@ :function:::void:do_qb_shra:int rd, int rt, int shift, int round { int i, j; - signed8 q0; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + int8_t q0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 8, v1 >>= 8) { - q0 = (signed8)(v1 & 0xff); + q0 = (int8_t)(v1 & 0xff); if (shift != 0) { if (round == 1 && (q0 & (1 << (shift - 1)))) @@ -209,7 +209,7 @@ else q0 = q0 >> shift; } - result |= ((unsigned32)((unsigned8)q0) << i); + result |= ((uint32_t)((uint8_t)q0) << i); } GPR[rd] = EXTEND32 (result); } @@ -217,14 +217,14 @@ :function:::void:do_ph_shrl:int rd, int rt, int shift { int i, j; - unsigned16 h0; - unsigned32 v1 = GPR[rt]; - unsigned32 result = 0; + uint16_t h0; + uint32_t v1 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 16, v1 >>= 16) { - h0 = (unsigned16)(v1 & 0xffff); + h0 = (uint16_t)(v1 & 0xffff); h0 = h0 >> shift; - result |= ((unsigned32)h0 << i); + result |= ((uint32_t)h0 << i); } GPR[rd] = EXTEND32 (result); } @@ -234,24 +234,24 @@ :function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round { int i; - signed32 h0; - signed16 h1, h2; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - unsigned32 result = 0; + int32_t h0; + int16_t h1, h2; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + uint32_t result = 0; for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)(v2 & 0xffff); + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)(v2 & 0xffff); if (op == 0) // ADD - h0 = (signed32)h1 + (signed32)h2; + h0 = (int32_t)h1 + (int32_t)h2; else // SUB - h0 = (signed32)h1 - (signed32)h2; + h0 = (int32_t)h1 - (int32_t)h2; if (round == 1) h0 = (h0 + 1) >> 1; else h0 = h0 >> 1; - result |= ((unsigned32)((unsigned16)h0) << i); + result |= ((uint32_t)((uint16_t)h0) << i); } GPR[rd] = EXTEND32 (result); } @@ -261,13 +261,13 @@ :function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round { int i; - signed64 v0; - signed32 v1 = (signed32)GPR[rs]; - signed32 v2 = (signed32)GPR[rt]; + int64_t v0; + int32_t v1 = (int32_t)GPR[rs]; + int32_t v2 = (int32_t)GPR[rt]; if (op == 0) // ADD - v0 = (signed64)v1 + (signed64)v2; + v0 = (int64_t)v1 + (int64_t)v2; else // SUB - v0 = (signed64)v1 - (signed64)v2; + v0 = (int64_t)v1 - (int64_t)v2; if (round == 1) v0 = (v0 + 1) >> 1; else @@ -279,22 +279,22 @@ :function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)((v2 & 0xffff0000) >> 16); - result = (signed32)h1 * (signed32)h2; + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)((v2 & 0xffff0000) >> 16); + result = (int32_t)h1 * (int32_t)h2; if (op == 0) // DPAX - prod += (signed64)result; + prod += (int64_t)result; else // DPSX - prod -= (signed64)result; + prod -= (int64_t)result; } DSPLO(ac) = EXTEND32 (prod); DSPHI(ac) = EXTEND32 (prod >> 32); @@ -305,35 +305,35 @@ :function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat { int i; - unsigned32 v1 = GPR[rs]; - unsigned32 v2 = GPR[rt]; - signed16 h1, h2; - signed32 result; - unsigned32 lo = DSPLO(ac); - unsigned32 hi = DSPHI(ac); - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); - signed64 max, min; + uint32_t v1 = GPR[rs]; + uint32_t v2 = GPR[rt]; + int16_t h1, h2; + int32_t result; + uint32_t lo = DSPLO(ac); + uint32_t hi = DSPHI(ac); + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); + int64_t max, min; for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) { - h1 = (signed16)(v1 & 0xffff); - h2 = (signed16)((v2 & 0xffff0000) >> 16); - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + h1 = (int16_t)(v1 & 0xffff); + h2 = (int16_t)((v2 & 0xffff0000) >> 16); + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); result = 0x7fffffff; } else - result = ((signed32)h1 * (signed32)h2) << 1; + result = ((int32_t)h1 * (int32_t)h2) << 1; if (op == 0) // DPAQX - prod += (signed64)result; + prod += (int64_t)result; else // DPSQX - prod -= (signed64)result; + prod -= (int64_t)result; } // Saturation on the accumulator. if (sat == 1) { - max = (signed64) 0x7fffffffLL; - min = (signed64) 0xffffffff80000000LL; + max = (int64_t) 0x7fffffffLL; + min = (int64_t) 0xffffffff80000000LL; if (prod > max) { DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); diff --git a/sim/mips/interp.c b/sim/mips/interp.c index ede1e261d74..65015623ee5 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -718,7 +718,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, for (loop = 0; (loop < idt_monitor_size); loop += 4) { address_word vaddr = (idt_monitor_base + loop); - unsigned32 insn = (RSVD_INSTRUCTION | + uint32_t insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); H2T (insn); @@ -737,7 +737,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, unsigned loop; for (loop = 0; (loop < 24); loop++) { - unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ + uint32_t value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ switch (loop) { case 0: /* read */ @@ -787,7 +787,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, (pmon_monitor_base != 0) || (lsipmon_monitor_base != 0)) { - unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */, + uint32_t halt[2] = { 0x2404002f /* addiu r4, r0, 47 */, HALT_INSTRUCTION /* BREAK */ }; H2T (halt[0]); H2T (halt[1]); @@ -869,12 +869,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) if (length == 8) { cpu->fgr[rn - FGR_BASE] = - (unsigned32) T2H_8 (*(unsigned64*)memory); + (uint32_t) T2H_8 (*(uint64_t*)memory); return 8; } else { - cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory); + cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory); return 4; } } @@ -882,12 +882,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { if (length == 8) { - cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory); + cpu->fgr[rn - FGR_BASE] = T2H_8 (*(uint64_t*)memory); return 8; } else { - cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory); + cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory); return 4; } } @@ -898,12 +898,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) if (length == 8) { cpu->registers[rn] = - (unsigned32) T2H_8 (*(unsigned64*)memory); + (uint32_t) T2H_8 (*(uint64_t*)memory); return 8; } else { - cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); + cpu->registers[rn] = T2H_4 (*(uint32_t*)memory); return 4; } } @@ -911,12 +911,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { if (length == 8) { - cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); + cpu->registers[rn] = T2H_8 (*(uint64_t*)memory); return 8; } else { - cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory); + cpu->registers[rn] = (int32_t) T2H_4(*(uint32_t*)memory); return 4; } } @@ -943,13 +943,13 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { if (length == 8) { - *(unsigned64*)memory = - H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE])); + *(uint64_t*)memory = + H2T_8 ((uint32_t) (cpu->fgr[rn - FGR_BASE])); return 8; } else { - *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]); + *(uint32_t*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]); return 4; } } @@ -957,12 +957,12 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { if (length == 8) { - *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]); + *(uint64_t*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]); return 8; } else { - *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE])); + *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->fgr[rn - FGR_BASE])); return 4; } } @@ -972,13 +972,13 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { if (length == 8) { - *(unsigned64*)memory = - H2T_8 ((unsigned32) (cpu->registers[rn])); + *(uint64_t*)memory = + H2T_8 ((uint32_t) (cpu->registers[rn])); return 8; } else { - *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); + *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn])); return 4; } } @@ -986,13 +986,13 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { if (length == 8) { - *(unsigned64*)memory = - H2T_8 ((unsigned64) (cpu->registers[rn])); + *(uint64_t*)memory = + H2T_8 ((uint64_t) (cpu->registers[rn])); return 8; } else { - *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); + *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn])); return 4; } } @@ -1028,7 +1028,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, These addresses work as is on 64-bit targets but can be truncated for 32-bit targets. */ if (WITH_TARGET_WORD_BITSIZE == 32) - pc = (unsigned32) pc; + pc = (uint32_t) pc; CPU_PC_SET (cpu, pc); } @@ -2321,7 +2321,7 @@ decode_coproc (SIM_DESC sd, /* CPR[0,rd] = GPR[rt]; */ default: if (op == cp0_mfc0 || op == cp0_dmfc0) - GPR[rt] = (signed_word) (signed32) COP0_GPR[rd]; + GPR[rt] = (signed_word) (int32_t) COP0_GPR[rd]; else COP0_GPR[rd] = GPR[rt]; #if 0 @@ -2336,7 +2336,7 @@ decode_coproc (SIM_DESC sd, && rd == 16) { /* [D]MFC0 RT,C0_CONFIG,SEL */ - signed32 cfg = 0; + int32_t cfg = 0; switch (sel) { case 0: diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen index 3641e3652bc..1d53d187596 100644 --- a/sim/mips/m16.igen +++ b/sim/mips/m16.igen @@ -454,7 +454,7 @@ *mips16: *vr4100: { - unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2); + uint32_t temp = (basepc (SD_) & ~3) + (IMMED << 2); GPR[TRX] = EXTEND32 (temp); } @@ -463,7 +463,7 @@ *mips16: *vr4100: { - unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE); + uint32_t temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE); GPR[TRX] = EXTEND32 (temp); } diff --git a/sim/mips/m16e.igen b/sim/mips/m16e.igen index afd0e1f8f6c..cb894890670 100644 --- a/sim/mips/m16e.igen +++ b/sim/mips/m16e.igen @@ -55,7 +55,7 @@ *mips16e: { TRACE_ALU_INPUT1 (GPR[TRX]); - GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]); + GPR[TRX] = (unsigned_word)(uint8_t)(GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } @@ -64,7 +64,7 @@ *mips16e: { TRACE_ALU_INPUT1 (GPR[TRX]); - GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]); + GPR[TRX] = (unsigned_word)(uint16_t)(GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } @@ -74,7 +74,7 @@ { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT1 (GPR[TRX]); - GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]); + GPR[TRX] = (unsigned_word)(uint32_t)(GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } diff --git a/sim/mips/mdmx.c b/sim/mips/mdmx.c index 41830ecb769..e355da9193b 100644 --- a/sim/mips/mdmx.c +++ b/sim/mips/mdmx.c @@ -54,10 +54,10 @@ along with this program. If not, see . */ the (not guaranteed portable) assumption that right shifts of signed quantities in C do sign extension. */ -typedef unsigned64 unsigned48; +typedef uint64_t unsigned48; #define MASK48 (UNSIGNED64 (0xffffffffffff)) -typedef unsigned32 unsigned24; +typedef uint32_t unsigned24; #define MASK24 (UNSIGNED32 (0xffffff)) typedef enum { @@ -71,12 +71,12 @@ typedef enum { sel_imm /* immediate select */ } VT_select; -#define OB_MAX ((unsigned8)0xFF) -#define QH_MIN ((signed16)0x8000) -#define QH_MAX ((signed16)0x7FFF) +#define OB_MAX ((uint8_t)0xFF) +#define QH_MIN ((int16_t)0x8000) +#define QH_MAX ((int16_t)0x7FFF) -#define OB_CLAMP(x) ((unsigned8)((x) > OB_MAX ? OB_MAX : (x))) -#define QH_CLAMP(x) ((signed16)((x) < QH_MIN ? QH_MIN : \ +#define OB_CLAMP(x) ((uint8_t)((x) > OB_MAX ? OB_MAX : (x))) +#define QH_CLAMP(x) ((int16_t)((x) < QH_MIN ? QH_MIN : \ ((x) > QH_MAX ? QH_MAX : (x)))) #define MX_FMT(fmtsel) (((fmtsel) & 0x1) == 0 ? mdmx_ob : mdmx_qh) @@ -84,170 +84,170 @@ typedef enum { (((fmtsel) & 0x18) == 0x10 ? sel_vect : sel_imm)) #define QH_ELEM(v,fmtsel) \ - ((signed16)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF)) + ((int16_t)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF)) #define OB_ELEM(v,fmtsel) \ - ((unsigned8)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF)) + ((uint8_t)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF)) -typedef signed16 (*QH_FUNC)(signed16, signed16); -typedef unsigned8 (*OB_FUNC)(unsigned8, unsigned8); +typedef int16_t (*QH_FUNC)(int16_t, int16_t); +typedef uint8_t (*OB_FUNC)(uint8_t, uint8_t); /* vectorized logical operators */ -static signed16 -AndQH(signed16 ts, signed16 tt) +static int16_t +AndQH(int16_t ts, int16_t tt) { - return (signed16)((unsigned16)ts & (unsigned16)tt); + return (int16_t)((uint16_t)ts & (uint16_t)tt); } -static unsigned8 -AndOB(unsigned8 ts, unsigned8 tt) +static uint8_t +AndOB(uint8_t ts, uint8_t tt) { return ts & tt; } -static signed16 -NorQH(signed16 ts, signed16 tt) +static int16_t +NorQH(int16_t ts, int16_t tt) { - return (signed16)(((unsigned16)ts | (unsigned16)tt) ^ 0xFFFF); + return (int16_t)(((uint16_t)ts | (uint16_t)tt) ^ 0xFFFF); } -static unsigned8 -NorOB(unsigned8 ts, unsigned8 tt) +static uint8_t +NorOB(uint8_t ts, uint8_t tt) { return (ts | tt) ^ 0xFF; } -static signed16 -OrQH(signed16 ts, signed16 tt) +static int16_t +OrQH(int16_t ts, int16_t tt) { - return (signed16)((unsigned16)ts | (unsigned16)tt); + return (int16_t)((uint16_t)ts | (uint16_t)tt); } -static unsigned8 -OrOB(unsigned8 ts, unsigned8 tt) +static uint8_t +OrOB(uint8_t ts, uint8_t tt) { return ts | tt; } -static signed16 -XorQH(signed16 ts, signed16 tt) +static int16_t +XorQH(int16_t ts, int16_t tt) { - return (signed16)((unsigned16)ts ^ (unsigned16)tt); + return (int16_t)((uint16_t)ts ^ (uint16_t)tt); } -static unsigned8 -XorOB(unsigned8 ts, unsigned8 tt) +static uint8_t +XorOB(uint8_t ts, uint8_t tt) { return ts ^ tt; } -static signed16 -SLLQH(signed16 ts, signed16 tt) +static int16_t +SLLQH(int16_t ts, int16_t tt) { - unsigned32 s = (unsigned32)tt & 0xF; - return (signed16)(((unsigned32)ts << s) & 0xFFFF); + uint32_t s = (uint32_t)tt & 0xF; + return (int16_t)(((uint32_t)ts << s) & 0xFFFF); } -static unsigned8 -SLLOB(unsigned8 ts, unsigned8 tt) +static uint8_t +SLLOB(uint8_t ts, uint8_t tt) { - unsigned32 s = tt & 0x7; + uint32_t s = tt & 0x7; return (ts << s) & 0xFF; } -static signed16 -SRLQH(signed16 ts, signed16 tt) +static int16_t +SRLQH(int16_t ts, int16_t tt) { - unsigned32 s = (unsigned32)tt & 0xF; - return (signed16)((unsigned16)ts >> s); + uint32_t s = (uint32_t)tt & 0xF; + return (int16_t)((uint16_t)ts >> s); } -static unsigned8 -SRLOB(unsigned8 ts, unsigned8 tt) +static uint8_t +SRLOB(uint8_t ts, uint8_t tt) { - unsigned32 s = tt & 0x7; + uint32_t s = tt & 0x7; return ts >> s; } /* Vectorized arithmetic operators. */ -static signed16 -AddQH(signed16 ts, signed16 tt) +static int16_t +AddQH(int16_t ts, int16_t tt) { - signed32 t = (signed32)ts + (signed32)tt; + int32_t t = (int32_t)ts + (int32_t)tt; return QH_CLAMP(t); } -static unsigned8 -AddOB(unsigned8 ts, unsigned8 tt) +static uint8_t +AddOB(uint8_t ts, uint8_t tt) { - unsigned32 t = (unsigned32)ts + (unsigned32)tt; + uint32_t t = (uint32_t)ts + (uint32_t)tt; return OB_CLAMP(t); } -static signed16 -SubQH(signed16 ts, signed16 tt) +static int16_t +SubQH(int16_t ts, int16_t tt) { - signed32 t = (signed32)ts - (signed32)tt; + int32_t t = (int32_t)ts - (int32_t)tt; return QH_CLAMP(t); } -static unsigned8 -SubOB(unsigned8 ts, unsigned8 tt) +static uint8_t +SubOB(uint8_t ts, uint8_t tt) { - signed32 t; - t = (signed32)ts - (signed32)tt; + int32_t t; + t = (int32_t)ts - (int32_t)tt; if (t < 0) t = 0; - return (unsigned8)t; + return (uint8_t)t; } -static signed16 -MinQH(signed16 ts, signed16 tt) +static int16_t +MinQH(int16_t ts, int16_t tt) { return (ts < tt ? ts : tt); } -static unsigned8 -MinOB(unsigned8 ts, unsigned8 tt) +static uint8_t +MinOB(uint8_t ts, uint8_t tt) { return (ts < tt ? ts : tt); } -static signed16 -MaxQH(signed16 ts, signed16 tt) +static int16_t +MaxQH(int16_t ts, int16_t tt) { return (ts > tt ? ts : tt); } -static unsigned8 -MaxOB(unsigned8 ts, unsigned8 tt) +static uint8_t +MaxOB(uint8_t ts, uint8_t tt) { return (ts > tt ? ts : tt); } -static signed16 -MulQH(signed16 ts, signed16 tt) +static int16_t +MulQH(int16_t ts, int16_t tt) { - signed32 t = (signed32)ts * (signed32)tt; + int32_t t = (int32_t)ts * (int32_t)tt; return QH_CLAMP(t); } -static unsigned8 -MulOB(unsigned8 ts, unsigned8 tt) +static uint8_t +MulOB(uint8_t ts, uint8_t tt) { - unsigned32 t = (unsigned32)ts * (unsigned32)tt; + uint32_t t = (uint32_t)ts * (uint32_t)tt; return OB_CLAMP(t); } /* "msgn" and "sra" are defined only for QH format. */ -static signed16 -MsgnQH(signed16 ts, signed16 tt) +static int16_t +MsgnQH(int16_t ts, int16_t tt) { - signed16 t; + int16_t t; if (ts < 0) t = (tt == QH_MIN ? QH_MAX : -tt); else if (ts == 0) @@ -257,26 +257,26 @@ MsgnQH(signed16 ts, signed16 tt) return t; } -static signed16 -SRAQH(signed16 ts, signed16 tt) +static int16_t +SRAQH(int16_t ts, int16_t tt) { - unsigned32 s = (unsigned32)tt & 0xF; - return (signed16)((signed32)ts >> s); + uint32_t s = (uint32_t)tt & 0xF; + return (int16_t)((int32_t)ts >> s); } /* "pabsdiff" and "pavg" are defined only for OB format. */ -static unsigned8 -AbsDiffOB(unsigned8 ts, unsigned8 tt) +static uint8_t +AbsDiffOB(uint8_t ts, uint8_t tt) { return (ts >= tt ? ts - tt : tt - ts); } -static unsigned8 -AvgOB(unsigned8 ts, unsigned8 tt) +static uint8_t +AvgOB(uint8_t ts, uint8_t tt) { - return ((unsigned32)ts + (unsigned32)tt + 1) >> 1; + return ((uint32_t)ts + (uint32_t)tt + 1) >> 1; } @@ -297,35 +297,35 @@ static const OB_FUNC ob_func[] = { /* Auxiliary functions for CPR updates. */ /* Vector mapping for QH format. */ -static unsigned64 -qh_vector_op(unsigned64 v1, unsigned64 v2, QH_FUNC func) +static uint64_t +qh_vector_op(uint64_t v1, uint64_t v2, QH_FUNC func) { - unsigned64 result = 0; + uint64_t result = 0; int i; - signed16 h, h1, h2; + int16_t h, h1, h2; for (i = 0; i < 64; i += 16) { - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; - h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; + h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16; h = (*func)(h1, h2); - result |= ((unsigned64)((unsigned16)h) << i); + result |= ((uint64_t)((uint16_t)h) << i); } return result; } -static unsigned64 -qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func) +static uint64_t +qh_map_op(uint64_t v1, int16_t h2, QH_FUNC func) { - unsigned64 result = 0; + uint64_t result = 0; int i; - signed16 h, h1; + int16_t h, h1; for (i = 0; i < 64; i += 16) { - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; h = (*func)(h1, h2); - result |= ((unsigned64)((unsigned16)h) << i); + result |= ((uint64_t)((uint16_t)h) << i); } return result; } @@ -333,51 +333,51 @@ qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func) /* Vector operations for OB format. */ -static unsigned64 -ob_vector_op(unsigned64 v1, unsigned64 v2, OB_FUNC func) +static uint64_t +ob_vector_op(uint64_t v1, uint64_t v2, OB_FUNC func) { - unsigned64 result = 0; + uint64_t result = 0; int i; - unsigned8 b, b1, b2; + uint8_t b, b1, b2; for (i = 0; i < 64; i += 8) { b1 = v1 & 0xFF; v1 >>= 8; b2 = v2 & 0xFF; v2 >>= 8; b = (*func)(b1, b2); - result |= ((unsigned64)b << i); + result |= ((uint64_t)b << i); } return result; } -static unsigned64 -ob_map_op(unsigned64 v1, unsigned8 b2, OB_FUNC func) +static uint64_t +ob_map_op(uint64_t v1, uint8_t b2, OB_FUNC func) { - unsigned64 result = 0; + uint64_t result = 0; int i; - unsigned8 b, b1; + uint8_t b, b1; for (i = 0; i < 64; i += 8) { b1 = v1 & 0xFF; v1 >>= 8; b = (*func)(b1, b2); - result |= ((unsigned64)b << i); + result |= ((uint64_t)b << i); } return result; } /* Primary entry for operations that update CPRs. */ -unsigned64 +uint64_t mdmx_cpr_op(sim_cpu *cpu, address_word cia, int op, - unsigned64 op1, + uint64_t op1, int vt, MX_fmtsel fmtsel) { - unsigned64 op2; - unsigned64 result = 0; + uint64_t op2; + uint64_t result = 0; switch (MX_FMT (fmtsel)) { @@ -422,16 +422,16 @@ mdmx_cpr_op(sim_cpu *cpu, /* Operations that update CCs */ static void -qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) +qh_vector_test(sim_cpu *cpu, uint64_t v1, uint64_t v2, int cond) { int i; - signed16 h1, h2; + int16_t h1, h2; int boolean; for (i = 0; i < 4; i++) { - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; - h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; + h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16; boolean = ((cond & MX_C_EQ) && (h1 == h2)) || ((cond & MX_C_LT) && (h1 < h2)); SETFCC(i, boolean); @@ -439,15 +439,15 @@ qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) } static void -qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond) +qh_map_test(sim_cpu *cpu, uint64_t v1, int16_t h2, int cond) { int i; - signed16 h1; + int16_t h1; int boolean; for (i = 0; i < 4; i++) { - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; boolean = ((cond & MX_C_EQ) && (h1 == h2)) || ((cond & MX_C_LT) && (h1 < h2)); SETFCC(i, boolean); @@ -455,10 +455,10 @@ qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond) } static void -ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) +ob_vector_test(sim_cpu *cpu, uint64_t v1, uint64_t v2, int cond) { int i; - unsigned8 b1, b2; + uint8_t b1, b2; int boolean; for (i = 0; i < 8; i++) @@ -472,15 +472,15 @@ ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) } static void -ob_map_test(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int cond) +ob_map_test(sim_cpu *cpu, uint64_t v1, uint8_t b2, int cond) { int i; - unsigned8 b1; + uint8_t b1; int boolean; for (i = 0; i < 8; i++) { - b1 = (unsigned8)(v1 & 0xFF); v1 >>= 8; + b1 = (uint8_t)(v1 & 0xFF); v1 >>= 8; boolean = ((cond & MX_C_EQ) && (b1 == b2)) || ((cond & MX_C_LT) && (b1 < b2)); SETFCC(i, boolean); @@ -492,11 +492,11 @@ void mdmx_cc_op(sim_cpu *cpu, address_word cia, int cond, - unsigned64 v1, + uint64_t v1, int vt, MX_fmtsel fmtsel) { - unsigned64 op2; + uint64_t op2; switch (MX_FMT (fmtsel)) { @@ -538,89 +538,89 @@ mdmx_cc_op(sim_cpu *cpu, /* Pick operations. */ -static unsigned64 -qh_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf) +static uint64_t +qh_vector_pick(sim_cpu *cpu, uint64_t v1, uint64_t v2, int tf) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - unsigned16 h; + uint16_t h; s = 0; for (i = 0; i < 4; i++) { h = ((GETFCC(i) == tf) ? (v1 & 0xFFFF) : (v2 & 0xFFFF)); v1 >>= 16; v2 >>= 16; - result |= ((unsigned64)h << s); + result |= ((uint64_t)h << s); s += 16; } return result; } -static unsigned64 -qh_map_pick(sim_cpu *cpu, unsigned64 v1, signed16 h2, int tf) +static uint64_t +qh_map_pick(sim_cpu *cpu, uint64_t v1, int16_t h2, int tf) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - unsigned16 h; + uint16_t h; s = 0; for (i = 0; i < 4; i++) { - h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (unsigned16)h2; + h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (uint16_t)h2; v1 >>= 16; - result |= ((unsigned64)h << s); + result |= ((uint64_t)h << s); s += 16; } return result; } -static unsigned64 -ob_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf) +static uint64_t +ob_vector_pick(sim_cpu *cpu, uint64_t v1, uint64_t v2, int tf) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - unsigned8 b; + uint8_t b; s = 0; for (i = 0; i < 8; i++) { b = (GETFCC(i) == tf) ? (v1 & 0xFF) : (v2 & 0xFF); v1 >>= 8; v2 >>= 8; - result |= ((unsigned64)b << s); + result |= ((uint64_t)b << s); s += 8; } return result; } -static unsigned64 -ob_map_pick(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int tf) +static uint64_t +ob_map_pick(sim_cpu *cpu, uint64_t v1, uint8_t b2, int tf) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - unsigned8 b; + uint8_t b; s = 0; for (i = 0; i < 8; i++) { b = (GETFCC(i) == tf) ? (v1 & 0xFF) : b2; v1 >>= 8; - result |= ((unsigned64)b << s); + result |= ((uint64_t)b << s); s += 8; } return result; } -unsigned64 +uint64_t mdmx_pick_op(sim_cpu *cpu, address_word cia, int tf, - unsigned64 v1, + uint64_t v1, int vt, MX_fmtsel fmtsel) { - unsigned64 result = 0; - unsigned64 op2; + uint64_t result = 0; + uint64_t op2; switch (MX_FMT (fmtsel)) { @@ -663,111 +663,111 @@ mdmx_pick_op(sim_cpu *cpu, /* Accumulators. */ -typedef void (*QH_ACC)(signed48 *a, signed16 ts, signed16 tt); +typedef void (*QH_ACC)(signed48 *a, int16_t ts, int16_t tt); static void -AccAddAQH(signed48 *a, signed16 ts, signed16 tt) +AccAddAQH(signed48 *a, int16_t ts, int16_t tt) { *a += (signed48)ts + (signed48)tt; } static void -AccAddLQH(signed48 *a, signed16 ts, signed16 tt) +AccAddLQH(signed48 *a, int16_t ts, int16_t tt) { *a = (signed48)ts + (signed48)tt; } static void -AccMulAQH(signed48 *a, signed16 ts, signed16 tt) +AccMulAQH(signed48 *a, int16_t ts, int16_t tt) { *a += (signed48)ts * (signed48)tt; } static void -AccMulLQH(signed48 *a, signed16 ts, signed16 tt) +AccMulLQH(signed48 *a, int16_t ts, int16_t tt) { *a = (signed48)ts * (signed48)tt; } static void -SubMulAQH(signed48 *a, signed16 ts, signed16 tt) +SubMulAQH(signed48 *a, int16_t ts, int16_t tt) { *a -= (signed48)ts * (signed48)tt; } static void -SubMulLQH(signed48 *a, signed16 ts, signed16 tt) +SubMulLQH(signed48 *a, int16_t ts, int16_t tt) { *a = -((signed48)ts * (signed48)tt); } static void -AccSubAQH(signed48 *a, signed16 ts, signed16 tt) +AccSubAQH(signed48 *a, int16_t ts, int16_t tt) { *a += (signed48)ts - (signed48)tt; } static void -AccSubLQH(signed48 *a, signed16 ts, signed16 tt) +AccSubLQH(signed48 *a, int16_t ts, int16_t tt) { *a = (signed48)ts - (signed48)tt; } -typedef void (*OB_ACC)(signed24 *acc, unsigned8 ts, unsigned8 tt); +typedef void (*OB_ACC)(signed24 *acc, uint8_t ts, uint8_t tt); static void -AccAddAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccAddAOB(signed24 *a, uint8_t ts, uint8_t tt) { *a += (signed24)ts + (signed24)tt; } static void -AccAddLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccAddLOB(signed24 *a, uint8_t ts, uint8_t tt) { *a = (signed24)ts + (signed24)tt; } static void -AccMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccMulAOB(signed24 *a, uint8_t ts, uint8_t tt) { *a += (signed24)ts * (signed24)tt; } static void -AccMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccMulLOB(signed24 *a, uint8_t ts, uint8_t tt) { *a = (signed24)ts * (signed24)tt; } static void -SubMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +SubMulAOB(signed24 *a, uint8_t ts, uint8_t tt) { *a -= (signed24)ts * (signed24)tt; } static void -SubMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +SubMulLOB(signed24 *a, uint8_t ts, uint8_t tt) { *a = -((signed24)ts * (signed24)tt); } static void -AccSubAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccSubAOB(signed24 *a, uint8_t ts, uint8_t tt) { *a += (signed24)ts - (signed24)tt; } static void -AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccSubLOB(signed24 *a, uint8_t ts, uint8_t tt) { *a = (signed24)ts - (signed24)tt; } static void -AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt) +AccAbsDiffOB(signed24 *a, uint8_t ts, uint8_t tt) { - unsigned8 t = (ts >= tt ? ts - tt : tt - ts); + uint8_t t = (ts >= tt ? ts - tt : tt - ts); *a += (signed24)t; } @@ -788,37 +788,37 @@ static const OB_ACC ob_acc[] = { static void -qh_vector_acc(signed48 a[], unsigned64 v1, unsigned64 v2, QH_ACC acc) +qh_vector_acc(signed48 a[], uint64_t v1, uint64_t v2, QH_ACC acc) { int i; - signed16 h1, h2; + int16_t h1, h2; for (i = 0; i < 4; i++) { - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; - h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; + h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16; (*acc)(&a[i], h1, h2); } } static void -qh_map_acc(signed48 a[], unsigned64 v1, signed16 h2, QH_ACC acc) +qh_map_acc(signed48 a[], uint64_t v1, int16_t h2, QH_ACC acc) { int i; - signed16 h1; + int16_t h1; for (i = 0; i < 4; i++) { - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; (*acc)(&a[i], h1, h2); } } static void -ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc) +ob_vector_acc(signed24 a[], uint64_t v1, uint64_t v2, OB_ACC acc) { int i; - unsigned8 b1, b2; + uint8_t b1, b2; for (i = 0; i < 8; i++) { @@ -829,10 +829,10 @@ ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc) } static void -ob_map_acc(signed24 a[], unsigned64 v1, unsigned8 b2, OB_ACC acc) +ob_map_acc(signed24 a[], uint64_t v1, uint8_t b2, OB_ACC acc) { int i; - unsigned8 b1; + uint8_t b1; for (i = 0; i < 8; i++) { @@ -847,11 +847,11 @@ void mdmx_acc_op(sim_cpu *cpu, address_word cia, int op, - unsigned64 op1, + uint64_t op1, int vt, MX_fmtsel fmtsel) { - unsigned64 op2; + uint64_t op2; switch (MX_FMT (fmtsel)) { @@ -893,13 +893,13 @@ mdmx_acc_op(sim_cpu *cpu, /* Reading and writing accumulator (no conversion). */ -unsigned64 +uint64_t mdmx_rac_op(sim_cpu *cpu, address_word cia, int op, int fmt) { - unsigned64 result; + uint64_t result; unsigned int shift; int i; @@ -934,8 +934,8 @@ void mdmx_wacl(sim_cpu *cpu, address_word cia, int fmt, - unsigned64 vs, - unsigned64 vt) + uint64_t vs, + uint64_t vt) { int i; @@ -944,7 +944,7 @@ mdmx_wacl(sim_cpu *cpu, case MX_FMT_QH: for (i = 0; i < 4; i++) { - signed32 s = (signed16)(vs & 0xFFFF); + int32_t s = (int16_t)(vs & 0xFFFF); ACC.qh[i] = ((signed48)s << 16) | (vt & 0xFFFF); vs >>= 16; vt >>= 16; } @@ -952,7 +952,7 @@ mdmx_wacl(sim_cpu *cpu, case MX_FMT_OB: for (i = 0; i < 8; i++) { - signed16 s = (signed8)(vs & 0xFF); + int16_t s = (int8_t)(vs & 0xFF); ACC.ob[i] = ((signed24)s << 8) | (vt & 0xFF); vs >>= 8; vt >>= 8; } @@ -966,7 +966,7 @@ void mdmx_wach(sim_cpu *cpu, address_word cia, int fmt, - unsigned64 vs) + uint64_t vs) { int i; @@ -975,7 +975,7 @@ mdmx_wach(sim_cpu *cpu, case MX_FMT_QH: for (i = 0; i < 4; i++) { - signed32 s = (signed16)(vs & 0xFFFF); + int32_t s = (int16_t)(vs & 0xFFFF); ACC.qh[i] &= ~((signed48)0xFFFF << 32); ACC.qh[i] |= ((signed48)s << 32); vs >>= 16; @@ -998,16 +998,16 @@ mdmx_wach(sim_cpu *cpu, /* Reading and writing accumulator (rounding conversions). Enumerating function guarantees s >= 0 for QH ops. */ -typedef signed16 (*QH_ROUND)(signed48 a, signed16 s); +typedef int16_t (*QH_ROUND)(signed48 a, int16_t s); #define QH_BIT(n) ((unsigned48)1 << (n)) #define QH_ONES(n) (((unsigned48)1 << (n))-1) -static signed16 -RNASQH(signed48 a, signed16 s) +static int16_t +RNASQH(signed48 a, int16_t s) { signed48 t; - signed16 result = 0; + int16_t result = 0; if (s > 48) result = 0; @@ -1031,16 +1031,16 @@ RNASQH(signed48 a, signed16 s) if (t < QH_MIN) t = QH_MIN; } - result = (signed16)t; + result = (int16_t)t; } return result; } -static signed16 -RNAUQH(signed48 a, signed16 s) +static int16_t +RNAUQH(signed48 a, int16_t s) { unsigned48 t; - signed16 result; + int16_t result; if (s > 48) result = 0; @@ -1053,16 +1053,16 @@ RNAUQH(signed48 a, signed16 s) t++; if (t > 0xFFFF) t = 0xFFFF; - result = (signed16)t; + result = (int16_t)t; } return result; } -static signed16 -RNESQH(signed48 a, signed16 s) +static int16_t +RNESQH(signed48 a, int16_t s) { signed48 t; - signed16 result = 0; + int16_t result = 0; if (s > 47) result = 0; @@ -1086,16 +1086,16 @@ RNESQH(signed48 a, signed16 s) if (t < QH_MIN) t = QH_MIN; } - result = (signed16)t; + result = (int16_t)t; } return result; } -static signed16 -RNEUQH(signed48 a, signed16 s) +static int16_t +RNEUQH(signed48 a, int16_t s) { unsigned48 t; - signed16 result; + int16_t result; if (s > 48) result = 0; @@ -1113,16 +1113,16 @@ RNEUQH(signed48 a, signed16 s) } if (t > 0xFFFF) t = 0xFFFF; - result = (signed16)t; + result = (int16_t)t; } return result; } -static signed16 -RZSQH(signed48 a, signed16 s) +static int16_t +RZSQH(signed48 a, int16_t s) { signed48 t; - signed16 result = 0; + int16_t result = 0; if (s > 47) result = 0; @@ -1139,16 +1139,16 @@ RZSQH(signed48 a, signed16 s) if (t < QH_MIN) t = QH_MIN; } - result = (signed16)t; + result = (int16_t)t; } return result; } -static signed16 -RZUQH(signed48 a, signed16 s) +static int16_t +RZUQH(signed48 a, int16_t s) { unsigned48 t; - signed16 result = 0; + int16_t result = 0; if (s > 48) result = 0; @@ -1159,21 +1159,21 @@ RZUQH(signed48 a, signed16 s) t = ((unsigned48)a & MASK48) >> s; if (t > 0xFFFF) t = 0xFFFF; - result = (signed16)t; + result = (int16_t)t; } return result; } -typedef unsigned8 (*OB_ROUND)(signed24 a, unsigned8 s); +typedef uint8_t (*OB_ROUND)(signed24 a, uint8_t s); #define OB_BIT(n) ((unsigned24)1 << (n)) #define OB_ONES(n) (((unsigned24)1 << (n))-1) -static unsigned8 -RNAUOB(signed24 a, unsigned8 s) +static uint8_t +RNAUOB(signed24 a, uint8_t s) { - unsigned8 result; + uint8_t result; unsigned24 t; if (s > 24) @@ -1190,10 +1190,10 @@ RNAUOB(signed24 a, unsigned8 s) return result; } -static unsigned8 -RNEUOB(signed24 a, unsigned8 s) +static uint8_t +RNEUOB(signed24 a, uint8_t s) { - unsigned8 result; + uint8_t result; unsigned24 t; if (s > 24) @@ -1215,10 +1215,10 @@ RNEUOB(signed24 a, unsigned8 s) return result; } -static unsigned8 -RZUOB(signed24 a, unsigned8 s) +static uint8_t +RZUOB(signed24 a, uint8_t s) { - unsigned8 result; + uint8_t result; unsigned24 t; if (s >= 24) @@ -1241,17 +1241,17 @@ static const OB_ROUND ob_round[] = { }; -static unsigned64 -qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round) +static uint64_t +qh_vector_round(sim_cpu *cpu, address_word cia, uint64_t v2, QH_ROUND round) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - signed16 h, h2; + int16_t h, h2; s = 0; for (i = 0; i < 4; i++) { - h2 = (signed16)(v2 & 0xFFFF); + h2 = (int16_t)(v2 & 0xFFFF); if (h2 >= 0) h = (*round)(ACC.qh[i], h2); else @@ -1260,18 +1260,18 @@ qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round) h = 0xdead; } v2 >>= 16; - result |= ((unsigned64)((unsigned16)h) << s); + result |= ((uint64_t)((uint16_t)h) << s); s += 16; } return result; } -static unsigned64 -qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round) +static uint64_t +qh_map_round(sim_cpu *cpu, address_word cia, int16_t h2, QH_ROUND round) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - signed16 h; + int16_t h; s = 0; for (i = 0; i < 4; i++) @@ -1283,57 +1283,57 @@ qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round) UnpredictableResult (); h = 0xdead; } - result |= ((unsigned64)((unsigned16)h) << s); + result |= ((uint64_t)((uint16_t)h) << s); s += 16; } return result; } -static unsigned64 -ob_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, OB_ROUND round) +static uint64_t +ob_vector_round(sim_cpu *cpu, address_word cia, uint64_t v2, OB_ROUND round) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - unsigned8 b, b2; + uint8_t b, b2; s = 0; for (i = 0; i < 8; i++) { b2 = v2 & 0xFF; v2 >>= 8; b = (*round)(ACC.ob[i], b2); - result |= ((unsigned64)b << s); + result |= ((uint64_t)b << s); s += 8; } return result; } -static unsigned64 -ob_map_round(sim_cpu *cpu, address_word cia, unsigned8 b2, OB_ROUND round) +static uint64_t +ob_map_round(sim_cpu *cpu, address_word cia, uint8_t b2, OB_ROUND round) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; - unsigned8 b; + uint8_t b; s = 0; for (i = 0; i < 8; i++) { b = (*round)(ACC.ob[i], b2); - result |= ((unsigned64)b << s); + result |= ((uint64_t)b << s); s += 8; } return result; } -unsigned64 +uint64_t mdmx_round_op(sim_cpu *cpu, address_word cia, int rm, int vt, MX_fmtsel fmtsel) { - unsigned64 op2; - unsigned64 result = 0; + uint64_t op2; + uint64_t result = 0; switch (MX_FMT (fmtsel)) { @@ -1409,14 +1409,14 @@ static const sh_map qh_shuffle[][4] = { }; -unsigned64 +uint64_t mdmx_shuffle(sim_cpu *cpu, address_word cia, int shop, - unsigned64 op1, - unsigned64 op2) + uint64_t op1, + uint64_t op2) { - unsigned64 result = 0; + uint64_t result = 0; int i, s; int op; @@ -1426,7 +1426,7 @@ mdmx_shuffle(sim_cpu *cpu, s = 0; for (i = 0; i < 4; i++) { - unsigned64 v; + uint64_t v; switch (qh_shuffle[op][i].source) { @@ -1450,7 +1450,7 @@ mdmx_shuffle(sim_cpu *cpu, s = 0; for (i = 0; i < 8; i++) { - unsigned8 b; + uint8_t b; unsigned int ishift = 8*ob_shuffle[op][i].index; switch (ob_shuffle[op][i].source) @@ -1468,7 +1468,7 @@ mdmx_shuffle(sim_cpu *cpu, Unpredictable (); b = 0; } - result |= ((unsigned64)b << s); + result |= ((uint64_t)b << s); s += 8; } } diff --git a/sim/mips/mdmx.igen b/sim/mips/mdmx.igen index fb9bef3bac1..0fd870c09f5 100644 --- a/sim/mips/mdmx.igen +++ b/sim/mips/mdmx.igen @@ -188,7 +188,7 @@ *mdmx: *sb1: { - unsigned64 result; + uint64_t result; int s; check_mdmx (SD_, instruction_0); check_mdmx_fmtop (SD_, instruction_0, FMTOP); @@ -205,7 +205,7 @@ *mdmx: *sb1: { - unsigned64 result; + uint64_t result; int s; check_mdmx (SD_, instruction_0); check_mdmx_fmtop (SD_, instruction_0, FMTOP); diff --git a/sim/mips/micromips.igen b/sim/mips/micromips.igen index b2ebe2fc7f9..acbff6f2db2 100644 --- a/sim/mips/micromips.igen +++ b/sim/mips/micromips.igen @@ -81,7 +81,7 @@ } -:function:::unsigned32:compute_movep_src_reg:int reg +:function:::uint32_t:compute_movep_src_reg:int reg *micromips32: *micromips64: { @@ -99,7 +99,7 @@ } } -:function:::unsigned32:compute_andi16_imm:int encoded_imm +:function:::uint32_t:compute_andi16_imm:int encoded_imm *micromips32: *micromips64: { diff --git a/sim/mips/micromipsdsp.igen b/sim/mips/micromipsdsp.igen index e00a3fc97ae..a68d25007b8 100644 --- a/sim/mips/micromipsdsp.igen +++ b/sim/mips/micromipsdsp.igen @@ -169,7 +169,7 @@ "bposge32 " *micromipsdsp: { - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; if (pos >= 32) NIA = delayslot_micromips (SD_, NIA + (EXTEND12 (IMMEDIATE) << 1), NIA, MICROMIPS_DELAYSLOT_SIZE_ANY); diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index a033fce9d04..c5db5c2304f 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -161,7 +161,7 @@ Programmers Volume III, Revision 0.95, section 4.9. */ if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) == (ksu_user << status_KSU_shift)) - return (address_word)((signed32)base + (signed32)offset); + return (address_word)((int32_t)base + (int32_t)offset); #endif return base + offset; } @@ -263,7 +263,7 @@ // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo // to check for restrictions (2) and (3) above. // -:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new +:function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new { if (history->mf.timestamp + 3 > time) { @@ -289,7 +289,7 @@ *vr4100: *vr5000: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = check_mf_cycles (SD_, history, time, "MT"); history->mt.timestamp = time; history->mt.cia = CIA; @@ -300,7 +300,7 @@ *mipsIV: *mipsV: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) || check_mf_cycles (SD_, history, time, "MT")); history->mt.timestamp = time; @@ -317,7 +317,7 @@ *micromips32: *micromips64: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); history->mt.timestamp = time; history->mt.cia = CIA; return 1; @@ -345,7 +345,7 @@ *micromips32: *micromips64: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = 1; if (peer != NULL && peer->mt.timestamp > history->op.timestamp @@ -383,7 +383,7 @@ *vr4100: *vr5000: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = (check_mf_cycles (SD_, hi, time, "OP") && check_mf_cycles (SD_, lo, time, "OP")); hi->op.timestamp = time; @@ -397,7 +397,7 @@ *mipsIV: *mipsV: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) || (check_mf_cycles (SD_, hi, time, "OP") && check_mf_cycles (SD_, lo, time, "OP"))); @@ -418,7 +418,7 @@ *micromips64: { /* FIXME: could record the fact that a stall occured if we want */ - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); hi->op.timestamp = time; lo->op.timestamp = time; hi->op.cia = CIA; @@ -440,7 +440,7 @@ *vr5000: *r3900: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = (check_mf_cycles (SD_, hi, time, "OP") && check_mf_cycles (SD_, lo, time, "OP")); hi->op.timestamp = time; @@ -454,7 +454,7 @@ *mipsIV: *mipsV: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) || (check_mf_cycles (SD_, hi, time, "OP") && check_mf_cycles (SD_, lo, time, "OP"))); @@ -473,7 +473,7 @@ *micromips32: *micromips64: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); hi->op.timestamp = time; lo->op.timestamp = time; hi->op.cia = CIA; @@ -538,7 +538,7 @@ TRACE_ALU_RESULT (GPR[rd]); } -:function:::void:do_addi:int rs, int rt, unsigned16 immediate +:function:::void:do_addi:int rs, int rt, uint16_t immediate { if (NotWordValue (GPR[rs])) Unpredictable (); @@ -592,7 +592,7 @@ { int s = 32 + shift; TRACE_ALU_INPUT2 (GPR[rt], s); - GPR[rd] = ((signed64) GPR[rt]) >> s; + GPR[rd] = ((int64_t) GPR[rt]) >> s; TRACE_ALU_RESULT (GPR[rd]); } @@ -600,7 +600,7 @@ { int s = 32 + shift; TRACE_ALU_INPUT2 (GPR[rt], s); - GPR[rd] = (unsigned64) GPR[rt] >> s; + GPR[rd] = (uint64_t) GPR[rt] >> s; TRACE_ALU_RESULT (GPR[rd]); } @@ -655,12 +655,12 @@ :function:::void:do_clo:int rd, int rs { - unsigned32 temp = GPR[rs]; - unsigned32 i, mask; + uint32_t temp = GPR[rs]; + uint32_t i, mask; if (NotWordValue (GPR[rs])) Unpredictable (); TRACE_ALU_INPUT1 (GPR[rs]); - for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) + for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) { if ((temp & mask) == 0) break; @@ -672,12 +672,12 @@ :function:::void:do_clz:int rd, int rs { - unsigned32 temp = GPR[rs]; - unsigned32 i, mask; + uint32_t temp = GPR[rs]; + uint32_t i, mask; if (NotWordValue (GPR[rs])) Unpredictable (); TRACE_ALU_INPUT1 (GPR[rs]); - for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) + for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) { if ((temp & mask) != 0) break; @@ -689,11 +689,11 @@ :function:::void:do_dclo:int rd, int rs { - unsigned64 temp = GPR[rs]; - unsigned32 i; - unsigned64 mask; + uint64_t temp = GPR[rs]; + uint32_t i; + uint64_t mask; TRACE_ALU_INPUT1 (GPR[rs]); - for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) + for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) { if ((temp & mask) == 0) break; @@ -705,11 +705,11 @@ :function:::void:do_dclz:int rd, int rs { - unsigned64 temp = GPR[rs]; - unsigned32 i; - unsigned64 mask; + uint64_t temp = GPR[rs]; + uint32_t i; + uint64_t mask; TRACE_ALU_INPUT1 (GPR[rs]); - for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) + for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) { if ((temp & mask) != 0) break; @@ -791,9 +791,9 @@ } else { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + uint64_t memval = 0; + uint64_t memval1 = 0; + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); unsigned int shift = 2; unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); @@ -823,8 +823,8 @@ } else { - unsigned64 memval = 0; - unsigned64 memval1 = 0; + uint64_t memval = 0; + uint64_t memval1 = 0; LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr, isDATA, isREAL); GPR[rt] = memval; @@ -842,13 +842,13 @@ :function:::void:do_madd:int rs, int rt { - signed64 temp; + int64_t temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); + + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); LO = EXTEND32 (temp); HI = EXTEND32 (VH4_8 (temp)); TRACE_ALU_RESULT2 (HI, LO); @@ -856,14 +856,14 @@ :function:::void:do_dsp_madd:int ac, int rs, int rt { - signed64 temp; + int64_t temp; if (ac == 0) check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) - + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); + + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); DSPLO(ac) = EXTEND32 (temp); DSPHI(ac) = EXTEND32 (VH4_8 (temp)); if (ac == 0) @@ -872,13 +872,13 @@ :function:::void:do_maddu:int rs, int rt { - unsigned64 temp; + uint64_t temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); + + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ LO = EXTEND32 (temp); HI = EXTEND32 (VH4_8 (temp)); @@ -887,14 +887,14 @@ :function:::void:do_dsp_maddu:int ac, int rs, int rt { - unsigned64 temp; + uint64_t temp; if (ac == 0) check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) - + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); + + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); if (ac == 0) ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ DSPLO(ac) = EXTEND32 (temp); @@ -939,13 +939,13 @@ :function:::void:do_msub:int rs, int rt { - signed64 temp; + int64_t temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); + - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); LO = EXTEND32 (temp); HI = EXTEND32 (VH4_8 (temp)); TRACE_ALU_RESULT2 (HI, LO); @@ -953,14 +953,14 @@ :function:::void:do_dsp_msub:int ac, int rs, int rt { - signed64 temp; + int64_t temp; if (ac == 0) check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) - - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); + - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); DSPLO(ac) = EXTEND32 (temp); DSPHI(ac) = EXTEND32 (VH4_8 (temp)); if (ac == 0) @@ -969,13 +969,13 @@ :function:::void:do_msubu:int rs, int rt { - unsigned64 temp; + uint64_t temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); + - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); LO = EXTEND32 (temp); HI = EXTEND32 (VH4_8 (temp)); TRACE_ALU_RESULT2 (HI, LO); @@ -983,14 +983,14 @@ :function:::void:do_dsp_msubu:int ac, int rs, int rt { - unsigned64 temp; + uint64_t temp; if (ac == 0) check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) - - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); + - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); DSPLO(ac) = EXTEND32 (temp); DSPHI(ac) = EXTEND32 (VH4_8 (temp)); if (ac == 0) @@ -1025,26 +1025,26 @@ :function:::void:do_mul:int rd, int rs, int rt { - signed64 prod; + int64_t prod; if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = (((signed64)(signed32) GPR[rs]) - * ((signed64)(signed32) GPR[rt])); + prod = (((int64_t)(int32_t) GPR[rs]) + * ((int64_t)(int32_t) GPR[rt])); GPR[rd] = EXTEND32 (VL4_8 (prod)); TRACE_ALU_RESULT (GPR[rd]); } :function:::void:do_dsp_mult:int ac, int rs, int rt { - signed64 prod; + int64_t prod; if (ac == 0) check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = ((signed64)(signed32) GPR[rs]) - * ((signed64)(signed32) GPR[rt]); + prod = ((int64_t)(int32_t) GPR[rs]) + * ((int64_t)(int32_t) GPR[rt]); DSPLO(ac) = EXTEND32 (VL4_8 (prod)); DSPHI(ac) = EXTEND32 (VH4_8 (prod)); if (ac == 0) @@ -1056,14 +1056,14 @@ :function:::void:do_dsp_multu:int ac, int rs, int rt { - unsigned64 prod; + uint64_t prod; if (ac == 0) check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = ((unsigned64)(unsigned32) GPR[rs]) - * ((unsigned64)(unsigned32) GPR[rt]); + prod = ((uint64_t)(uint32_t) GPR[rs]) + * ((uint64_t)(uint32_t) GPR[rt]); DSPLO(ac) = EXTEND32 (VL4_8 (prod)); DSPHI(ac) = EXTEND32 (VH4_8 (prod)); if (ac == 0) @@ -1083,7 +1083,7 @@ :function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0 { - unsigned32 instruction = instruction_0; + uint32_t instruction = instruction_0; address_word base = GPR[basereg]; address_word offset = EXTEND16 (offsetarg); { @@ -1097,9 +1097,9 @@ } else { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + uint64_t memval = 0; + uint64_t memval1 = 0; + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); address_word bigendiancpu = @@ -1107,7 +1107,7 @@ unsigned int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); byte = ((vaddr & mask) ^ bigendiancpu); - memval = ((unsigned64) GPR[rt] << (8 * byte)); + memval = ((uint64_t) GPR[rt] << (8 * byte)); if (LLBIT) StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL); @@ -1131,8 +1131,8 @@ } else { - unsigned64 memval = 0; - unsigned64 memval1 = 0; + uint64_t memval = 0; + uint64_t memval1 = 0; memval = GPR[rt]; if (LLBIT) StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr, @@ -1248,9 +1248,9 @@ :function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0 { - unsigned64 fsx; - unsigned64 ftx; - unsigned64 fdx; + uint64_t fsx; + uint64_t ftx; + uint64_t fdx; check_fpu (SD_); check_u64 (SD_, instruction_0); fsx = ValueFPR (fs, fmt_ps); @@ -1493,7 +1493,7 @@ } else { - unsigned64 fdx; + uint64_t fdx; fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd, fmt_ps)), PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd, @@ -1730,9 +1730,9 @@ } else { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + uint64_t memval = 0; + uint64_t memval1 = 0; + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); address_word bigendiancpu = @@ -1740,7 +1740,7 @@ unsigned int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); byte = ((vaddr & mask) ^ bigendiancpu); - memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); + memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte)); StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL); } @@ -1794,7 +1794,7 @@ -:function:::void:do_addiu:int rs, int rt, unsigned16 immediate +:function:::void:do_addiu:int rs, int rt, uint16_t immediate { if (NotWordValue (GPR[rs])) Unpredictable (); @@ -2395,7 +2395,7 @@ -:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate +:function:::void:do_daddiu:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); GPR[rt] = GPR[rs] + EXTEND16 (immediate); @@ -2474,10 +2474,10 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - signed64 n = GPR[rs]; - signed64 d = GPR[rt]; - signed64 hi; - signed64 lo; + int64_t n = GPR[rs]; + int64_t d = GPR[rt]; + int64_t hi; + int64_t lo; if (d == 0) { lo = SIGNED64 (0x8000000000000000); @@ -2520,10 +2520,10 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - unsigned64 n = GPR[rs]; - unsigned64 d = GPR[rt]; - unsigned64 hi; - unsigned64 lo; + uint64_t n = GPR[rs]; + uint64_t d = GPR[rt]; + uint64_t hi; + uint64_t lo; if (d == 0) { lo = SIGNED64 (0x8000000000000000); @@ -2559,8 +2559,8 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - signed32 n = GPR[rs]; - signed32 d = GPR[rt]; + int32_t n = GPR[rs]; + int32_t d = GPR[rt]; if (d == 0) { LO = EXTEND32 (0x80000000); @@ -2605,8 +2605,8 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - unsigned32 n = GPR[rs]; - unsigned32 d = GPR[rt]; + uint32_t n = GPR[rs]; + uint32_t d = GPR[rt]; if (d == 0) { LO = EXTEND32 (0x80000000); @@ -2642,47 +2642,47 @@ :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p { - unsigned64 lo; - unsigned64 hi; - unsigned64 m00; - unsigned64 m01; - unsigned64 m10; - unsigned64 m11; - unsigned64 mid; + uint64_t lo; + uint64_t hi; + uint64_t m00; + uint64_t m01; + uint64_t m10; + uint64_t m11; + uint64_t mid; int sign; - unsigned64 op1 = GPR[rs]; - unsigned64 op2 = GPR[rt]; + uint64_t op1 = GPR[rs]; + uint64_t op2 = GPR[rt]; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); /* make signed multiply unsigned */ sign = 0; if (signed_p) { - if ((signed64) op1 < 0) + if ((int64_t) op1 < 0) { op1 = - op1; ++sign; } - if ((signed64) op2 < 0) + if ((int64_t) op2 < 0) { op2 = - op2; ++sign; } } /* multiply out the 4 sub products */ - m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); - m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); - m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); - m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); + m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2)); + m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2)); + m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2)); + m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2)); /* add the products */ - mid = ((unsigned64) VH4_8 (m00) - + (unsigned64) VL4_8 (m10) - + (unsigned64) VL4_8 (m01)); + mid = ((uint64_t) VH4_8 (m00) + + (uint64_t) VL4_8 (m10) + + (uint64_t) VL4_8 (m01)); lo = U8_4 (mid, m00); hi = (m11 - + (unsigned64) VH4_8 (mid) - + (unsigned64) VH4_8 (m01) - + (unsigned64) VH4_8 (m10)); + + (uint64_t) VH4_8 (mid) + + (uint64_t) VH4_8 (m01) + + (uint64_t) VH4_8 (m10)); /* fix the sign */ if (sign & 1) { @@ -2757,9 +2757,9 @@ } -:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y +:function:::uint64_t:do_dror:uint64_t x,uint64_t y { - unsigned64 result; + uint64_t result; y &= 63; TRACE_ALU_INPUT2 (x, y); @@ -2860,7 +2860,7 @@ :function:::void:do_dsra:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); - GPR[rd] = ((signed64) GPR[rt]) >> shift; + GPR[rd] = ((int64_t) GPR[rt]) >> shift; TRACE_ALU_RESULT (GPR[rd]); } @@ -2899,7 +2899,7 @@ { int s = MASKED64 (GPR[rs], 5, 0); TRACE_ALU_INPUT2 (GPR[rt], s); - GPR[rd] = ((signed64) GPR[rt]) >> s; + GPR[rd] = ((int64_t) GPR[rt]) >> s; TRACE_ALU_RESULT (GPR[rd]); } @@ -2920,7 +2920,7 @@ :function:::void:do_dsrl:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); - GPR[rd] = (unsigned64) GPR[rt] >> shift; + GPR[rd] = (uint64_t) GPR[rt] >> shift; TRACE_ALU_RESULT (GPR[rd]); } @@ -2959,7 +2959,7 @@ { int s = MASKED64 (GPR[rs], 5, 0); TRACE_ALU_INPUT2 (GPR[rt], s); - GPR[rd] = (unsigned64) GPR[rt] >> s; + GPR[rd] = (uint64_t) GPR[rt] >> s; TRACE_ALU_RESULT (GPR[rd]); } @@ -3126,7 +3126,7 @@ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; address_word paddr; - unsigned64 memval; + uint64_t memval; address_word vaddr; paddr = vaddr = loadstore_ea (SD_, base, offset); @@ -3148,7 +3148,7 @@ unsigned int byte; unsigned int word; address_word paddr; - unsigned64 memval; + uint64_t memval; address_word vaddr; int nr_lhs_bits; int nr_rhs_bits; @@ -3168,8 +3168,8 @@ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", - (long) ((unsigned64) vaddr >> 32), (long) vaddr, - (long) ((unsigned64) paddr >> 32), (long) paddr, + (long) ((uint64_t) vaddr >> 32), (long) vaddr, + (long) ((uint64_t) paddr >> 32), (long) paddr, word, byte, nr_lhs_bits, nr_rhs_bits); */ LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL); @@ -3187,9 +3187,9 @@ rt = (rt & ~lhs_mask) | (temp & lhs_mask); /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", - (long) ((unsigned64) memval >> 32), (long) memval, - (long) ((unsigned64) temp >> 32), (long) temp, - (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, + (long) ((uint64_t) memval >> 32), (long) memval, + (long) ((uint64_t) temp >> 32), (long) temp, + (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask, (long) (rt >> 32), (long) rt); */ return rt; } @@ -3201,7 +3201,7 @@ address_word bigendiancpu = (BigEndianCPU ? -1 : 0); unsigned int byte; address_word paddr; - unsigned64 memval; + uint64_t memval; address_word vaddr; paddr = vaddr = loadstore_ea (SD_, base, offset); @@ -3763,13 +3763,13 @@ :function:::void:do_mult:int rs, int rt, int rd { - signed64 prod; + int64_t prod; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = (((signed64)(signed32) GPR[rs]) - * ((signed64)(signed32) GPR[rt])); + prod = (((int64_t)(int32_t) GPR[rs]) + * ((int64_t)(int32_t) GPR[rt])); LO = EXTEND32 (VL4_8 (prod)); HI = EXTEND32 (VH4_8 (prod)); ACX = 0; /* SmartMIPS */ @@ -3816,13 +3816,13 @@ :function:::void:do_multu:int rs, int rt, int rd { - unsigned64 prod; + uint64_t prod; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = (((unsigned64)(unsigned32) GPR[rs]) - * ((unsigned64)(unsigned32) GPR[rt])); + prod = (((uint64_t)(uint32_t) GPR[rs]) + * ((uint64_t)(uint32_t) GPR[rt])); LO = EXTEND32 (VL4_8 (prod)); HI = EXTEND32 (VH4_8 (prod)); if (rd != 0) @@ -3959,9 +3959,9 @@ } -:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y +:function:::uint64_t:do_ror:uint32_t x,uint32_t y { - unsigned64 result; + uint64_t result; y &= 31; TRACE_ALU_INPUT2 (x, y); @@ -4000,7 +4000,7 @@ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; address_word paddr; - unsigned64 memval; + uint64_t memval; address_word vaddr; paddr = vaddr = loadstore_ea (SD_, base, offset); @@ -4022,7 +4022,7 @@ unsigned int byte; unsigned int word; address_word paddr; - unsigned64 memval; + uint64_t memval; address_word vaddr; int nr_lhs_bits; int nr_rhs_bits; @@ -4039,8 +4039,8 @@ nr_rhs_bits = 8 * access - 8 * byte; /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", - (long) ((unsigned64) vaddr >> 32), (long) vaddr, - (long) ((unsigned64) paddr >> 32), (long) paddr, + (long) ((uint64_t) vaddr >> 32), (long) vaddr, + (long) ((uint64_t) paddr >> 32), (long) paddr, word, byte, nr_lhs_bits, nr_rhs_bits); */ if (word == 0) @@ -4052,8 +4052,8 @@ memval = (rt << nr_lhs_bits); } /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", - (long) ((unsigned64) rt >> 32), (long) rt, - (long) ((unsigned64) memval >> 32), (long) memval); */ + (long) ((uint64_t) rt >> 32), (long) rt, + (long) ((uint64_t) memval >> 32), (long) memval); */ StoreMemory (byte, memval, 0, paddr, vaddr, isREAL); } @@ -4064,7 +4064,7 @@ address_word bigendiancpu = (BigEndianCPU ? -1 : 0); unsigned int byte; address_word paddr; - unsigned64 memval; + uint64_t memval; address_word vaddr; paddr = vaddr = loadstore_ea (SD_, base, offset); @@ -4212,7 +4212,7 @@ :function:::void:do_sll:int rt, int rd, int shift { - unsigned32 temp = (GPR[rt] << shift); + uint32_t temp = (GPR[rt] << shift); TRACE_ALU_INPUT2 (GPR[rt], shift); GPR[rd] = EXTEND32 (temp); TRACE_ALU_RESULT (GPR[rd]); @@ -4255,7 +4255,7 @@ :function:::void:do_sllv:int rs, int rt, int rd { int s = MASKED (GPR[rs], 4, 0); - unsigned32 temp = (GPR[rt] << s); + uint32_t temp = (GPR[rt] << s); TRACE_ALU_INPUT2 (GPR[rt], s); GPR[rd] = EXTEND32 (temp); TRACE_ALU_RESULT (GPR[rd]); @@ -4306,7 +4306,7 @@ } -:function:::void:do_slti:int rs, int rt, unsigned16 immediate +:function:::void:do_slti:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); @@ -4332,7 +4332,7 @@ } -:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate +:function:::void:do_sltiu:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); @@ -4387,7 +4387,7 @@ :function:::void:do_sra:int rt, int rd, int shift { - signed32 temp = (signed32) GPR[rt] >> shift; + int32_t temp = (int32_t) GPR[rt] >> shift; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], shift); @@ -4418,7 +4418,7 @@ :function:::void:do_srav:int rs, int rt, int rd { int s = MASKED (GPR[rs], 4, 0); - signed32 temp = (signed32) GPR[rt] >> s; + int32_t temp = (int32_t) GPR[rt] >> s; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], s); @@ -4448,7 +4448,7 @@ :function:::void:do_srl:int rt, int rd, int shift { - unsigned32 temp = (unsigned32) GPR[rt] >> shift; + uint32_t temp = (uint32_t) GPR[rt] >> shift; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], shift); @@ -4478,7 +4478,7 @@ :function:::void:do_srlv:int rs, int rt, int rd { int s = MASKED (GPR[rs], 4, 0); - unsigned32 temp = (unsigned32) GPR[rt] >> s; + uint32_t temp = (uint32_t) GPR[rt] >> s; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], s); @@ -4896,7 +4896,7 @@ } -:function:::void:do_xori:int rs, int rt, unsigned16 immediate +:function:::void:do_xori:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], immediate); GPR[rt] = GPR[rs] ^ immediate; @@ -5060,7 +5060,7 @@ // unsigned_word, which is limited to the size of the machine's registers. // -:function:::unsigned64:do_load_double:address_word base, address_word offset +:function:::uint64_t:do_load_double:address_word base, address_word offset *mipsII: *mips32: *mips32r2: @@ -5069,8 +5069,8 @@ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; address_word paddr; - unsigned64 memval; - unsigned64 v; + uint64_t memval; + uint64_t v; paddr = vaddr = loadstore_ea (SD_, base, offset); if ((vaddr & AccessLength_DOUBLEWORD) != 0) @@ -5080,7 +5080,7 @@ sim_core_unaligned_signal); } LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL); - v = (unsigned64)memval; + v = (uint64_t)memval; LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA, isREAL); return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); @@ -5094,7 +5094,7 @@ // unsigned_word, which is limited to the size of the machine's registers. // -:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v +:function:::void:do_store_double:address_word base, address_word offset, uint64_t v *mipsII: *mips32: *mips32r2: @@ -5103,7 +5103,7 @@ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; address_word paddr; - unsigned64 memval; + uint64_t memval; paddr = vaddr = loadstore_ea (SD_, base, offset); if ((vaddr & AccessLength_DOUBLEWORD) != 0) @@ -5504,7 +5504,7 @@ "dmfc1 r, f" *mipsIII: { - unsigned64 v; + uint64_t v; check_fpu (SD_); check_u64 (SD_, instruction_0); if (SizeFGR () == 64) @@ -5537,7 +5537,7 @@ "dmtc1 r, f" *mipsIII: { - unsigned64 v; + uint64_t v; check_fpu (SD_); check_u64 (SD_, instruction_0); if (SizeFGR () == 64) @@ -5724,7 +5724,7 @@ *mipsII: *mipsIII: { - unsigned64 v; + uint64_t v; check_fpu (SD_); v = EXTEND32 (FGR[FS]); PENDING_FILL (RT, v); diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen index be0772bf874..e0b838c4df2 100644 --- a/sim/mips/mips3264r2.igen +++ b/sim/mips/mips3264r2.igen @@ -21,7 +21,7 @@ :function:::void:do_dsbh:int rd, int rt { - union { unsigned64 d; unsigned16 h[4]; } u; + union { uint64_t d; uint16_t h[4]; } u; TRACE_ALU_INPUT1 (GPR[rt]); u.d = GPR[rt]; u.h[0] = SWAP_2 (u.h[0]); @@ -34,7 +34,7 @@ :function:::void:do_dshd:int rd, int rt { - unsigned64 d; + uint64_t d; TRACE_ALU_INPUT1 (GPR[rt]); d = GPR[rt]; GPR[rd] = ((d >> 48) @@ -181,7 +181,7 @@ :function:::void:do_wsbh:int rd, int rt { - union { unsigned32 w; unsigned16 h[2]; } u; + union { uint32_t w; uint16_t h[2]; } u; TRACE_ALU_INPUT1 (GPR[rt]); u.w = GPR[rt]; u.h[0] = SWAP_2 (u.h[0]); diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c index 876593b33f8..250310eceb3 100644 --- a/sim/mips/sim-main.c +++ b/sim/mips/sim-main.c @@ -254,7 +254,7 @@ store_memory (SIM_DESC SD, } -INLINE_SIM_MAIN (unsigned32) +INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC SD, sim_cpu *CPU, address_word cia, @@ -267,7 +267,7 @@ ifetch32 (SIM_DESC SD, address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; address_word paddr = vaddr; - unsigned64 memval; + uint64_t memval; if ((vaddr & access) != 0) SignalExceptionInstructionFetch (); @@ -278,7 +278,7 @@ ifetch32 (SIM_DESC SD, } -INLINE_SIM_MAIN (unsigned16) +INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC SD, sim_cpu *CPU, address_word cia, @@ -291,7 +291,7 @@ ifetch16 (SIM_DESC SD, address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; address_word paddr = vaddr; - unsigned64 memval; + uint64_t memval; if ((vaddr & access) != 0) SignalExceptionInstructionFetch (); @@ -433,18 +433,18 @@ pending_tick (SIM_DESC SD, { case 4: if (PENDING_SLOT_VALUE[index]) - *(unsigned32*)PENDING_SLOT_DEST[index] |= + *(uint32_t*)PENDING_SLOT_DEST[index] |= BIT32 (PENDING_SLOT_BIT[index]); else - *(unsigned32*)PENDING_SLOT_DEST[index] &= + *(uint32_t*)PENDING_SLOT_DEST[index] &= BIT32 (PENDING_SLOT_BIT[index]); break; case 8: if (PENDING_SLOT_VALUE[index]) - *(unsigned64*)PENDING_SLOT_DEST[index] |= + *(uint64_t*)PENDING_SLOT_DEST[index] |= BIT64 (PENDING_SLOT_BIT[index]); else - *(unsigned64*)PENDING_SLOT_DEST[index] &= + *(uint64_t*)PENDING_SLOT_DEST[index] &= BIT64 (PENDING_SLOT_BIT[index]); break; } @@ -452,11 +452,11 @@ pending_tick (SIM_DESC SD, switch (PENDING_SLOT_SIZE[index]) { case 4: - *(unsigned32*)PENDING_SLOT_DEST[index] = + *(uint32_t*)PENDING_SLOT_DEST[index] = PENDING_SLOT_VALUE[index]; break; case 8: - *(unsigned64*)PENDING_SLOT_DEST[index] = + *(uint64_t*)PENDING_SLOT_DEST[index] = PENDING_SLOT_VALUE[index]; break; } diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index faba1166800..d724688a434 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -33,8 +33,8 @@ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ER /* Deprecated macros and types for manipulating 64bit values. Use ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ -typedef signed64 word64; -typedef unsigned64 uword64; +typedef int64_t word64; +typedef uint64_t uword64; #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) @@ -115,7 +115,7 @@ typedef enum { more details. */ typedef struct _hilo_access { - signed64 timestamp; + int64_t timestamp; address_word cia; } hilo_access; @@ -135,7 +135,7 @@ typedef struct _hilo_history { #define ALU32_END(ANS) \ if (ALU32_HAD_OVERFLOW) \ SignalExceptionIntegerOverflow (); \ - (ANS) = (signed32) ALU32_OVERFLOW_RESULT + (ANS) = (int32_t) ALU32_OVERFLOW_RESULT #define ALU64_END(ANS) \ @@ -163,7 +163,7 @@ typedef struct _pending_write_queue { int slot_size[PSLOTS]; int slot_bit[PSLOTS]; void *slot_dest[PSLOTS]; - unsigned64 slot_value[PSLOTS]; + uint64_t slot_value[PSLOTS]; } pending_write_queue; #ifndef PENDING_TRACE @@ -243,8 +243,8 @@ enum float_operation 32 or 64 bits. Since the accumulators are 2's complement with overflow suppressed, high-order bits can be ignored in most contexts. */ -typedef signed32 signed24; -typedef signed64 signed48; +typedef int32_t signed24; +typedef int64_t signed48; typedef union { signed24 ob[8]; @@ -700,15 +700,15 @@ int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); /* FPR access. */ -unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats); +uint64_t value_fpr (SIM_STATE, int fpr, FP_formats); #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) -void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value); +void store_fpr (SIM_STATE, int fpr, FP_formats fmt, uint64_t value); #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) -unsigned64 ps_lower (SIM_STATE, unsigned64 op); +uint64_t ps_lower (SIM_STATE, uint64_t op); #define PSLower(op) ps_lower (SIM_ARGS, op) -unsigned64 ps_upper (SIM_STATE, unsigned64 op); +uint64_t ps_upper (SIM_STATE, uint64_t op); #define PSUpper(op) ps_upper (SIM_ARGS, op) -unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from); +uint64_t pack_ps (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats from); #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) @@ -722,41 +722,41 @@ void test_fcsr (SIM_STATE); /* FPU operations. */ -void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc); +void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, int abs, int cond, int cc); #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) -unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt); #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) -unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt); #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) -unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_add (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_sub (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt); #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) -unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt); #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) -unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt); #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) -unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2, - unsigned64 op3, FP_formats fmt); +uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2, + uint64_t op3, FP_formats fmt); #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) -unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2, - unsigned64 op3, FP_formats fmt); +uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2, + uint64_t op3, FP_formats fmt); #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) -unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2, - unsigned64 op3, FP_formats fmt); +uint64_t fp_nmadd (SIM_STATE, uint64_t op1, uint64_t op2, + uint64_t op3, FP_formats fmt); #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) -unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2, - unsigned64 op3, FP_formats fmt); +uint64_t fp_nmsub (SIM_STATE, uint64_t op1, uint64_t op2, + uint64_t op3, FP_formats fmt); #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) -unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to); +uint64_t convert (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to); #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) -unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, +uint64_t convert_ps (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to); #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) @@ -764,17 +764,17 @@ unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, /* MIPS-3D ASE operations. */ #define CompareAbs(op1,op2,fmt,cond,cc) \ fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) -unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_add_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_mul_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_recip1 (SIM_STATE, uint64_t op, FP_formats fmt); #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) -unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_recip2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) -unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); +uint64_t fp_rsqrt1 (SIM_STATE, uint64_t op, FP_formats fmt); #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) -unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +uint64_t fp_rsqrt2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) @@ -802,7 +802,7 @@ typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ #define MX_VECT_ABSD (13) /* SB-1 only. */ #define MX_VECT_AVG (14) /* SB-1 only. */ -unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); +uint64_t mdmx_cpr_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) @@ -822,10 +822,10 @@ unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmt #define MX_C_EQ 0x1 #define MX_C_LT 0x4 -void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel); +void mdmx_cc_op (SIM_STATE, int cond, uint64_t op1, int vt, MX_fmtsel fmtsel); #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) -unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel); +uint64_t mdmx_pick_op (SIM_STATE, int tf, uint64_t op1, int vt, MX_fmtsel fmtsel); #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) #define MX_VECT_ADDA (0) @@ -838,7 +838,7 @@ unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fm #define MX_VECT_SUBL (7) #define MX_VECT_ABSDA (8) /* SB-1 only. */ -void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); +void mdmx_acc_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) @@ -857,12 +857,12 @@ void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); #define MX_RAC_M (1) #define MX_RAC_H (2) -unsigned64 mdmx_rac_op (SIM_STATE, int, int); +uint64_t mdmx_rac_op (SIM_STATE, int, int); #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) -void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64); +void mdmx_wacl (SIM_STATE, int, uint64_t, uint64_t); #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) -void mdmx_wach (SIM_STATE, int, unsigned64); +void mdmx_wach (SIM_STATE, int, uint64_t); #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) #define MX_RND_AS (0) @@ -872,7 +872,7 @@ void mdmx_wach (SIM_STATE, int, unsigned64); #define MX_RND_ZS (4) #define MX_RND_ZU (5) -unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); +uint64_t mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) @@ -880,7 +880,7 @@ unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) -unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); +uint64_t mdmx_shuffle (SIM_STATE, int, uint64_t, uint64_t); #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) @@ -937,9 +937,9 @@ void unpredictable_action (sim_cpu *cpu, address_word cia); #define Unpredictable() unpredictable (SD_) #define UnpredictableResult() /* For now, do nothing. */ -INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); +INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) -INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); +INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) #define IMEM32_MICROMIPS(CIA) \ diff --git a/sim/mips/smartmips.igen b/sim/mips/smartmips.igen index 947568e0331..ef9bf81aaeb 100644 --- a/sim/mips/smartmips.igen +++ b/sim/mips/smartmips.igen @@ -31,8 +31,8 @@ "maddp r, r" *smartmips: { - unsigned64 res; - unsigned64 rs, rt; + uint64_t res; + uint64_t rs, rt; int i; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); @@ -83,8 +83,8 @@ "multp r, r" *smartmips: { - unsigned64 res; - unsigned64 rs, rt; + uint64_t res; + uint64_t rs, rt; int i; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); diff --git a/sim/mips/tx.igen b/sim/mips/tx.igen index c4cc524731d..2e84452ba10 100644 --- a/sim/mips/tx.igen +++ b/sim/mips/tx.igen @@ -8,9 +8,9 @@ "madd r, r, r" *r3900 { - signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - + ((signed64) EXTEND32 (GPR[RT]) - * (signed64) EXTEND32 (GPR[RS]))); + int64_t prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((int64_t) EXTEND32 (GPR[RT]) + * (int64_t) EXTEND32 (GPR[RS]))); check_mult_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); LO = EXTEND32 (prod); @@ -26,9 +26,9 @@ "maddu r, r, r" *r3900 { - unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - + ((unsigned64) VL4_8 (GPR[RS]) - * (unsigned64) VL4_8 (GPR[RT]))); + uint64_t prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((uint64_t) VL4_8 (GPR[RS]) + * (uint64_t) VL4_8 (GPR[RT]))); check_mult_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); LO = EXTEND32 (prod); diff --git a/sim/mips/vr.igen b/sim/mips/vr.igen index 9266ae6dc61..1d87da22535 100644 --- a/sim/mips/vr.igen +++ b/sim/mips/vr.igen @@ -40,7 +40,7 @@ // concatenation of the low 32 bits of HI and LO. :function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p { - unsigned64 lhs, x, y, xcut, ycut, product, result; + uint64_t lhs, x, y, xcut, ycut, product, result; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); @@ -82,10 +82,10 @@ /* Saturate the result to 32 bits. An unsigned, unsaturated result is zero-extended to 64 bits, but unsigned overflow causes all 64 bits to be set. */ - if (!unsigned_p && (unsigned64) EXTEND32 (result) != result) - result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff); + if (!unsigned_p && (uint64_t) EXTEND32 (result) != result) + result = ((int64_t) result < 0 ? -0x7fffffff - 1 : 0x7fffffff); else if (unsigned_p && (result >> 32) != 0) - result = (unsigned64) 0 - 1; + result = (uint64_t) 0 - 1; } TRACE_ALU_RESULT (result);