From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed, 1 Oct 2014 17:46:48 +0000 (-0700)
Subject: i965/fs: Use the actual regsister width in brw_reg_from_fs_reg
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b33e5465a7b62cfa05a29f163659ca60d30fe6c9;p=mesa.git

i965/fs: Use the actual regsister width in brw_reg_from_fs_reg

This fixes a bug where 1-wide operations don't properly translate down to
1-wide instructions.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index e20d3ccb8a4..c2010c036c9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1211,7 +1211,20 @@ brw_reg_from_fs_reg(fs_reg *reg)
    case MRF:
       if (reg->stride == 0) {
          brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
+      } else if (reg->width < 8) {
+         brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
+         brw_reg = stride(brw_reg, reg->width * reg->stride,
+                          reg->width, reg->stride);
       } else {
+         /* From the Haswell PRM:
+          *
+          * VertStride must be used to cross GRF register boundaries. This
+          * rule implies that elements within a 'Width' cannot cross GRF
+          * boundaries.
+          *
+          * So, for registers with width > 8, we have to use a width of 8
+          * and trust the compression state to sort out the exec size.
+          */
          brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
          brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
       }