From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 3 Jan 2022 22:33:39 +0000 (+0000)
Subject: sigh have to allow external clocks and reset mess even in microwatt-compat
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b35595829fb7e2390a28186008ab9df35131ea8e;p=soc.git

sigh have to allow external clocks and reset mess even in microwatt-compat
mode.  soc.vhdl still needs to be able to pull an external reset OR
DMI needs to be able to instruct the core to do it. hardly surprising
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 682e899d..088fa6e7 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -335,16 +335,24 @@ class TestIssuerBase(Elaboratable):
         # LoadStore1 and is already a submodule of LoadStore1
         if not isinstance(self.imem, ICache):
             m.submodules.imem = imem = csd(self.imem)
-        if self.microwatt_compat:
-            m.submodules.dbg = dbg = self.dbg
-        else:
-            m.submodules.dbg = dbg = dbd(self.dbg)
+        m.submodules.dbg = dbg = dbd(self.dbg)
         if self.jtag_en:
             m.submodules.jtag = jtag = dbd(self.jtag)
             # TODO: UART2GDB mux, here, from external pin
             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
             sync += dbg.dmi.connect_to(jtag.dmi)
 
+        # fixup the clocks in microwatt-compat mode (but leave resets alone
+        # so that microwatt soc.vhdl can pull a reset on the core or DMI
+        # can do it, just like in TestIssuer)
+        if self.microwatt_compat:
+            intclk = ClockSignal(self.core_domain)
+            dbgclk = ClockSignal(self.dbg_domain)
+            if self.core_domain != 'sync':
+                comb += intclk.eq(ClockSignal())
+            if self.dbg_domain != 'sync':
+                comb += dbgclk.eq(ClockSignal())
+
         cur_state = self.cur_state
 
         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 0ff83d69..7eb75f93 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -124,8 +124,8 @@ if __name__ == '__main__':
                          microwatt_compat=args.mwcompat, # microwatt compatible
                          units=units,
                          msr_reset=msr_reset)
-    if args.mwcompat:
-        pspec.core_domain = 'sync'
+    #if args.mwcompat:
+    #    pspec.core_domain = 'sync'
 
     print("mmu", pspec.__dict__["microwatt_mmu"])
     print("nocore", pspec.__dict__["nocore"])