From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 6 Sep 2019 09:56:42 +0000 (+0200)
Subject: soc_core: add JTAG UART support (uart_name="jtag_uart)
X-Git-Tag: 24jan2021_ls180~1023
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b356204f952f2184d168d35f026db5200d18c4a7;p=litex.git

soc_core: add JTAG UART support (uart_name="jtag_uart)
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index e46e7c61..a8832da0 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -318,6 +318,9 @@ class SoCCore(Module):
                 if uart_name == "jtag_atlantic":
                     from litex.soc.cores.jtag import JTAGAtlantic
                     self.submodules.uart_phy = JTAGAtlantic()
+                elif uart_name == "jtag_uart":
+                    from litex.soc.cores.jtag import JTAGPHY
+                    self.submodules.uart_phy = JTAGPHY(device=platform.device)
                 else:
                     self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
                 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))