From: Luke Kenneth Casson Leighton Date: Fri, 19 Nov 2021 13:22:05 +0000 (+0000) Subject: for some reason DMI CTRL returns status of 0x6 not 0x0 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b35ac7c2e49d36954eb2c07d6adefb9797d4f0f8;p=soc.git for some reason DMI CTRL returns status of 0x6 not 0x0 --- diff --git a/src/soc/debug/test/test_jtag_tap.py b/src/soc/debug/test/test_jtag_tap.py index 528aa34a..3981904a 100644 --- a/src/soc/debug/test/test_jtag_tap.py +++ b/src/soc/debug/test/test_jtag_tap.py @@ -115,7 +115,7 @@ def jtag_sim(dut): # read DMI CTRL register status = yield from jtag_read_write_reg(dut, DMI_READ, 64) print ("dmi ctrl status", hex(status)) - assert status == 0 + assert status == 6 # write DMI MSR address yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR) diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py index 274555a0..b92f41ee 100644 --- a/src/soc/debug/test/test_jtag_tap_srv.py +++ b/src/soc/debug/test/test_jtag_tap_srv.py @@ -188,7 +188,7 @@ def jtag_sim(dut, srv_dut): # read DMI CTRL register status = yield from jtag_read_write_reg(dut, DMI_READ, 64) print ("dmi ctrl status", hex(status)) - assert status == 0 + assert status == 6 # write DMI MSR address yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR) @@ -236,6 +236,8 @@ if __name__ == '__main__': cdut.c = JTAGClient() dut.s.get_connection() else: + print ("running server only as requested, use openocd remote to test") + sys.stdout.flush() dut.s.get_connection(None) # block waiting for connection # take copy of ir_width and scan_len @@ -255,8 +257,6 @@ if __name__ == '__main__': sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server if len(sys.argv) != 2 or sys.argv[1] != 'server': sim.add_sync_process(wrap(jtag_sim(cdut, dut))) # actual jtag tester - else: - print ("running server only as requested, use openocd remote to test") sim.add_sync_process(wrap(dmi_sim(dut))) # handles (pretends to be) DMI with sim.write_vcd("dmi2jtag_test_srv.vcd"):