From: lkcl <lkcl@web>
Date: Sun, 26 Mar 2023 12:10:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls001_v3~55
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b35b0ebe29b6433933b2f636a3d1e38fd757cd3b;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn
index 2566c0f65..ffeaa893c 100644
--- a/openpower/sv/rfc/ls008.mdwn
+++ b/openpower/sv/rfc/ls008.mdwn
@@ -65,17 +65,41 @@
 **Keywords**:
 
 ```
-    Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
-    Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model
+    Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
+    Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
+    Digital Signal Processing (DSP)
 ```
 
 **Motivation**
 
-TODO
+Power ISA is synonymous with Supercomputing and the early Supercomputers
+(ETA-10, ILLIAC-IV, CDC200, Cray) had Vectorisation. It is therefore anomalous
+that Power ISA does not have Scalable Vectors, instead having the legacy
+"PackedSIMD" paradigm. Fortunately this presents
+the opportunity to modernise Power ISA learning from both past ISA features and
+mistakes placing it far above the top of Supercomputing for the next two decades
+and beyond.
 
 **Notes and Observations**:
 
-1. TODO
+1. SVP64 is very much designed for ultra-light-weight Embedded use-cases all the
+  way up to moving the bar of Supercomputing orders of magnitude above its present
+  perception, whilst retaining at all times the Sequential Programming Execution
+  Model.
+2. This proposal is the **base** for further Extensions.  These include
+  extending SVP64 onto the Scalar VSX instructions (with a **LONG TERM** view in 10+ years
+  to deprecating the PackedSIMD aspects of VSX), to be discussed at a later
+  time, the potential for extending VSX registers to 128 or beyond, and Arithmetic
+  operations to a runtime-selectable choice of 128-bit, 256-bit, 512-bit or 1024-bit.
+3. Massive reductions in instruction count of between 2x and 20x have been demonstrated
+  with SVP64, which is far beyond anything ever achieved by any *general-purpose*
+  ISA Extension added to any ISA in the history of Computing. Normal reductions
+  expected are of the order of 5 to 10% being considered a highly worthwhile exercise
+  to pursue inclusion. not fractions of former sizes.
+4. Other potential extensions include work inspired by EXTRA-V and Eth-Zurich "Snitch"
+  to reduce CPU workload by 95% in the case of EXTRA-V and power consumption by
+  85% in the case of Snitch.  Addition massive reductions from ZOLC Research are
+  also anticipated.
 
 **Changes**