From: lkcl <lkcl@web>
Date: Sun, 21 Aug 2022 16:52:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~801
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b36fd8d1079ce0fcd77eb3b13145b9c0664fef8c;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 4a15058a9..13b27ff73 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -909,7 +909,7 @@ Instructions are broken down by Register Profiles as listed in the
 following auto-generated page: [[opcode_regs_deduped]].  These tables,
 despite being auto-generated, are part of the Specification.
 
-# SV pseudocode illilustration
+# SV pseudocode illustration
 
 ## Single-predicated Instruction
 
@@ -927,8 +927,7 @@ overrides not included.  if there is no predicate, it is set to all 1s
         if (rd.isvec)  { id += 1; }
         if (rs1.isvec) { irs1 += 1; }
         if (rs2.isvec) { irs2 += 1; }
-        if (id == VL or irs1 == VL or irs2 == VL)
-        {
+        if (id == VL or irs1 == VL or irs2 == VL) {
           # end VL hardware loop
           STATE.srcoffs = 0; # reset
           return;