From: Ron Dreslinski <rdreslin@umich.edu>
Date: Wed, 14 Jan 2004 21:21:49 +0000 (-0500)
Subject: Add memory space implemented for range 0xffff00188
X-Git-Tag: m5_1.0_tutorial~421^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3788280f6e630e225fa7e4c666a8d2973227308;p=gem5.git

Add memory space implemented for range 0xffff00188

--HG--
extra : convert_revision : ce17505cb97bf9985fd1f4992df89113a5ea3bf5
---

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d934299b8..84b3d5840 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -90,8 +90,16 @@ AlphaTlb::checkCacheability(MemReqPtr req)
     if (req->paddr & PA_UNCACHED_BIT) {
         if (PA_IPR_SPACE(req->paddr)) {
             // IPR memory space not implemented
-            if (!req->xc->misspeculating())
-                panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+            if (!req->xc->misspeculating()) {
+                switch (req->paddr) {
+                  case 0xFFFFF00188:
+                    req->data = 0;
+                    break;
+
+                  default:
+                    panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+                }
+            }
         } else {
             // mark request as uncacheable
             req->flags |= UNCACHEABLE;