From: Samuel Pitoiset Date: Wed, 3 Oct 2018 14:09:24 +0000 (+0200) Subject: radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b38228ccb0e3a0874e8845a325a6b658bc2661ed;p=mesa.git radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK It has probably no effect without out of order rasterization anyway. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 6b3e120802e..2db44cb24fd 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1081,6 +1081,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ms->pa_sc_mode_cntl_1 = S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | + S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) | /* always 1: */ S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | @@ -1124,8 +1125,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, } if (out_of_order_rast) { - ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) | - S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7); + ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1); } if (vkms && vkms->pSampleMask) {