From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 8 Jan 2017 01:56:22 +0000 (-0800)
Subject: Make SIP.STIP read-only
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b387326dbc6b4bf2452191b6817529133ff362a5;p=riscv-isa-sim.git

Make SIP.STIP read-only

h/t Ron Minnich

See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f3764ae..75f4002 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -373,9 +373,10 @@ void processor_t::set_csr(int which, reg_t val)
                  | SSTATUS_XS | SSTATUS_PUM;
       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
-    case CSR_SIP:
-      return set_csr(CSR_MIP,
-                     (state.mip & ~state.mideleg) | (val & state.mideleg));
+    case CSR_SIP: {
+      reg_t mask = MIP_SSIP;
+      return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
+    }
     case CSR_SIE:
       return set_csr(CSR_MIE,
                      (state.mie & ~state.mideleg) | (val & state.mideleg));