From: Luke Kenneth Casson Leighton Date: Thu, 27 Oct 2022 14:47:53 +0000 (+0100) Subject: fix dsrd pseudocode for new 3-in 2-out X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b38b5537c70792eded9cf8dd02adce48355905d6;p=openpower-isa.git fix dsrd pseudocode for new 3-in 2-out https://bugs.libre-soc.org/show_bug.cgi?id=937#c16 --- diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn index c1f79c0b..63453354 100644 --- a/openpower/isa/svfixedarith.mdwn +++ b/openpower/isa/svfixedarith.mdwn @@ -74,13 +74,11 @@ VA2-Form Pseudo-code: - hi <- (RC) - lo <- (RA) - sh <- (RB) - n <- sh[58:63] - mask[0:63] <- MASK(0, 63 - n) - v[0:63] <- (hi & ¬mask) | (lo & mask) - RT <- ROTL64(v, 64 - n) + n <- (RB)[58:63] + v <- ROTL128((RA) || [0]*64, 64-n) + mask <- ¬MASK(n, 63) + RT <- v[0:63] | ((RC) & mask) + RS <- v[64:127] Special Registers Altered: diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index 21223be3..76d15496 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -51,45 +51,21 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsrd0(self): - prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,4,5,6"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 - gprs[3] = 0x123456789ABCDEF - gprs[4] = 0xFEDCBA9876543210 - gprs[5] = sh % 2 ** 64 - e = ExpectedState(pc=4, int_regs=gprs) - v = (gprs[3] << 64) | gprs[4] - v >>= sh % 64 - e.intregs[3] = v % 2 ** 64 - self.add_case(prog, gprs, expected=e) - - def case_dsrd1(self): - prog = Program(list(SVP64Asm(["dsrd 3,3,5,4"])), False) - for sh in _SHIFT_TEST_RANGE: - with self.subTest(sh=sh): - gprs = [0] * 32 - gprs[3] = 0x123456789ABCDEF + gprs[6] = 0x123456789ABCDEF gprs[4] = 0xFEDCBA9876543210 gprs[5] = sh % 2 ** 64 e = ExpectedState(pc=4, int_regs=gprs) - v = (gprs[4] << 64) | gprs[3] + v = (gprs[4] << 64) v >>= sh % 64 - e.intregs[3] = v % 2 ** 64 - self.add_case(prog, gprs, expected=e) - - def case_dsrd2(self): - prog = Program(list(SVP64Asm(["dsrd 3,5,3,4"])), False) - for sh in _SHIFT_TEST_RANGE: - with self.subTest(sh=sh): - gprs = [0] * 32 - gprs[3] = sh % 2 ** 64 - gprs[4] = 0xFEDCBA9876543210 - gprs[5] = 0x02468ACE13579BDF - e = ExpectedState(pc=4, int_regs=gprs) - v = (gprs[4] << 64) | gprs[5] - v >>= sh % 64 - e.intregs[3] = v % 2 ** 64 + mask = ~((2 ** 64 - 1) >> (sh%64)) + v |= (gprs[6] & mask) + print ("case_dsrd0", hex(mask), sh, hex(v)) + e.intregs[3] = v % 2 ** 64 + e.intregs[6] = (v >> 64) % 2 ** 64 self.add_case(prog, gprs, expected=e) @@ -224,7 +200,7 @@ class SVP64BigIntCases(TestAccumulatorBase): r4 (carry in at top-end) 0x1234 << 192 = r18 r17 r16 0x1234_0000_5678_0000 0x9ABC_0000_DEF0_0000 0x1357_0000_9BDF_0000 * - r4 (carry out i.e. scalar remainder) 0xFEDC + r4 (carry out i.e. scalar remainder) 0xFEDC """ prog = Program(list(SVP64Asm(["sv.divmod2du/mrr *16,*16,3,4"])), False) gprs = [0] * 32