From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 09:48:30 +0000 (+0100)
Subject: remove redundant imports
X-Git-Tag: ls180-24jan2020~652
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b398f8a6d352e2c6a1f186f6dc1b1af3935c6cfd;p=ieee754fpu.git

remove redundant imports
---

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 424d39e7..3cb26acf 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -41,7 +41,7 @@ RoundMod, FPAddStage0Mod etc.
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
+from nmutil.singlepipe import ControlBase
 from nmutil.multipipe import CombMuxOutPipe
 from nmutil.multipipe import PriorityCombMuxInPipe
 from nmutil.concurrentunit import ReservationStations, num_bits