From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Jul 2017 17:32:31 +0000 (+0200)
Subject: Fix handling of empty cell port assignments (i.e. ignore them)
X-Git-Tag: yosys-0.8~382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb;p=yosys.git

Fix handling of empty cell port assignments (i.e. ignore them)
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index d71e9c574..41c1cfded 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -640,6 +640,9 @@ struct HierarchyPass : public Pass {
 					if (w == nullptr || w->port_id == 0)
 						continue;
 
+					if (GetSize(conn.second) == 0)
+						continue;
+
 					if (GetSize(w) == GetSize(conn.second))
 						continue;
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e85714b57..ae89453d0 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -247,6 +247,9 @@ struct TechmapWorker
 				continue;
 			}
 
+			if (GetSize(it.second) == 0)
+				continue;
+
 			RTLIL::Wire *w = tpl->wires_.at(portname);
 			RTLIL::SigSig c, extra_connect;