From: lkcl <lkcl@web>
Date: Sat, 24 Sep 2022 23:19:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~306
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3c053e87ad79b5e8f89d7d354752118e2c011f8;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index b998e1c85..7c670a840 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -212,3 +212,12 @@ First we define the contents of 64-bit registers:
 |------|-------------------------|-----|---------------------------------|
 | bits | b0.b1.b2.b3.b4.b5.b6.b7 | ... | b56.b57.b58.b59.b60.b61.b62.b63 |
 | bytes|        B0               | ... |  B7                             |
+
+In pseudocode we may now define B0 to B7 in terms of b0..b63 and thus
+also define Registers:
+
+     B0 = b0 || b1 || b2 || b3 || b4 || b5 || b6 || b7
+     B1 = b8 || ..........                 ....  || b15
+     ...
+     B7 = b56 || .........                 ....  || b63
+     RA = B0 || B1 || B2 || B3 || B4 || B5 || B6 || B7