From: lkcl <lkcl@web>
Date: Mon, 3 Apr 2023 12:41:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~157
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3c66f97d0ceb85f2ffac3ddd6abb16fdd32d241;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 6486b075d..22daccc61 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -44,8 +44,10 @@ Table of contents
 Simple-V is a type of Vectorisation best described as a "Prefix Loop
 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and
 to the 8086 `REP` Prefix instruction.  More advanced features are similar
-to the Z80 `CPIR` instruction. If viewed one-dimensionally as an actual
-Vector ISA it introduces over 1.5 million 64-bit Vector instructions.
+to the Z80 `CPIR` instruction. If naively viewed one-dimensionally as an actual
+Vector ISA it introduces over 1.5 million 64-bit True-Scalable Vector instructions
+on the SFFS Subset and closer to 10 million 64-bit True-Scalable Vector
+instructions if introduced on VSX.
 SVP64, the instruction format used by Simple-V, is therefore best viewed
 as an orthogonal RISC-paradigm "Prefixing" subsystem instead.