From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Aug 2021 16:28:53 +0000 (+0100)
Subject: whoops test for sv.bc* matched accidentally, use explicit test
X-Git-Tag: xlen-bcd~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3d8993eddd626a16f6b98b633037ce222e4c6d6;p=openpower-isa.git

whoops test for sv.bc* matched accidentally, use explicit test
"svremap" and "svstate" instead
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 450f73f5..c0ef32f9 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1224,7 +1224,7 @@ class ISACaller:
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
         if (self.is_svp64_mode or ins_name == 'setvl' or
-           ins_name.startswith("sv")):
+           ins_name in ['svremap', 'svstate']):
             yield from self.svstate_pre_inc()
         if self.is_svp64_mode:
             pre = yield from self.update_new_svstate_steps()