From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Apr 2020 21:12:28 +0000 (-0700)
Subject: abc9_ops: fix bypass boxes using (* abc9_bypass *)
X-Git-Tag: working-ls180~549^2~20
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3e2538a140cac36c32b133d4475a052cfc46809;p=yosys.git

abc9_ops: fix bypass boxes using (* abc9_bypass *)
---

diff --git a/kernel/constids.inc b/kernel/constids.inc
index 6b40a5908..25996d2d8 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -2,10 +2,9 @@ X(A)
 X(abc9_box)
 X(abc9_box_id)
 X(abc9_box_seq)
+X(abc9_bypass)
 X(abc9_carry)
 X(abc9_flop)
-X(abc9_holes)
-X(abc9_init)
 X(abc9_lut)
 X(abc9_mergeability)
 X(abc9_scc)
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index d7280e3fd..37d0528c1 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -102,7 +102,7 @@ void check(RTLIL::Design *design, bool dff_mode)
 				auto inst_module = design->module(cell->type);
 				if (!inst_module)
 					continue;
-				if (!inst_module->attributes.count(ID::abc9_flop))
+				if (!inst_module->get_bool_attribute(ID::abc9_flop))
 					continue;
 				auto derived_type = inst_module->derive(design, cell->parameters);
 				if (!processed.insert(derived_type).second)
@@ -171,9 +171,9 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 			if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
 				continue;
 
-			if (inst_module->attributes.count(ID::abc9_flop) && !dff_mode)
+			if (inst_module->get_bool_attribute(ID::abc9_flop) && !dff_mode)
 				continue;
-			if (!inst_module->attributes.count(ID::abc9_box) && !inst_module->attributes.count(ID::abc9_flop))
+			if (!inst_module->get_bool_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_flop))
 				continue;
 
 			if (!unmap_design->module(derived_type)) {
@@ -205,13 +205,11 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 							break;
 						}
 
-					if (!found) {
-						derived_module->set_bool_attribute(ID::abc9_box, false);
-						log_assert(!derived_module->attributes.count(ID::abc9_box));
+					if (!found)
 						goto skip_cell;
-					}
 
 					derived_module->set_bool_attribute(ID::abc9_box, false);
+					derived_module->set_bool_attribute(ID::abc9_bypass);
 				}
 
 				if (derived_type != cell->type) {
@@ -265,9 +263,8 @@ void prep_bypass(RTLIL::Design *design)
 			auto derived_type = inst_module->derive(design, cell->parameters);
 			inst_module = design->module(derived_type);
 			log_assert(inst_module);
-			if (inst_module->get_blackbox_attribute(true /* ignore_wb */))
-				continue;
-			if (!inst_module->get_bool_attribute(ID::abc9_box))
+			log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
+			if (!inst_module->get_bool_attribute(ID::abc9_bypass))
 				continue;
 
 
@@ -444,7 +441,7 @@ void prep_dff(RTLIL::Design *design)
 			auto inst_module = design->module(cell->type);
 			if (!inst_module)
 				continue;
-			if (!inst_module->attributes.count(ID::abc9_flop))
+			if (!inst_module->get_bool_attribute(ID::abc9_flop))
 				continue;
 			auto derived_type = inst_module->derive(design, cell->parameters);
 			auto derived_module = design->module(derived_type);
@@ -589,7 +586,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			continue;
 
 		auto inst_module = design->module(cell->type);
-		bool abc9_flop = inst_module && inst_module->attributes.count(ID::abc9_flop);
+		bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
 		if (abc9_flop && !dff)
 			continue;