From: Jean THOMAS Date: Fri, 24 Jul 2020 14:42:53 +0000 (+0200) Subject: Remove unnecessary modules in gram tests X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3efdc9a842198f9d4516cc6f37f574a9b410af2;p=gram.git Remove unnecessary modules in gram tests --- diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py index c992057..1110054 100644 --- a/gram/test/test_compat.py +++ b/gram/test/test_compat.py @@ -57,8 +57,6 @@ class TimelineTestCase(FHDLTestCase): (10, sigB.eq(1)), (11, sigB.eq(0)), ]) - m = Module() - m.submodules.timeline = timeline def process(): # Test default value for unset signals @@ -100,7 +98,7 @@ class TimelineTestCase(FHDLTestCase): self.assertFalse((yield sigA)) self.assertFalse((yield sigB)) - runSimulation(m, process, "test_timeline.vcd") + runSimulation(timeline, process, "test_timeline.vcd") class RoundRobinOutputMatchSpec(Elaboratable): def __init__(self, dut): diff --git a/gram/test/test_core_multiplexer.py b/gram/test/test_core_multiplexer.py index 10d5f50..05e89c2 100644 --- a/gram/test/test_core_multiplexer.py +++ b/gram/test/test_core_multiplexer.py @@ -6,8 +6,7 @@ from utils import * class AntiStarvationTestCase(FHDLTestCase): def test_duration(self): def generic_test(timeout): - m = Module() - m.submodules = dut = _AntiStarvation(timeout) + dut = _AntiStarvation(timeout) def process(): yield dut.en.eq(1) @@ -21,7 +20,7 @@ class AntiStarvationTestCase(FHDLTestCase): self.assertTrue((yield dut.max_time)) - runSimulation(m, process, "test_core_multiplexer_antistarvation.vcd") + runSimulation(dut, process, "test_core_multiplexer_antistarvation.vcd") def test_formal(self): def generic_test(timeout): diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py index a1f9408..a968536 100644 --- a/gram/test/test_core_refresher.py +++ b/gram/test/test_core_refresher.py @@ -9,8 +9,7 @@ from utils import * class RefreshExecuterTestCase(FHDLTestCase): def test_executer(self): def generic_test(abits, babits, trp, trfc): - m = Module() - m.submodules.dut = dut = RefreshExecuter(abits=abits, babits=babits, trp=trp, trfc=trfc) + dut = RefreshExecuter(abits=abits, babits=babits, trp=trp, trfc=trfc) def process(): yield dut.start.eq(1) @@ -21,7 +20,7 @@ class RefreshExecuterTestCase(FHDLTestCase): yield self.assertEqual((yield dut.a), 0) - runSimulation(m, process, "test_refreshexecuter.vcd") + runSimulation(dut, process, "test_refreshexecuter.vcd") generic_test(20, 20, 5, 5) generic_test(20, 20, 100, 5) @@ -41,18 +40,16 @@ class RefreshTimerTestCase(FHDLTestCase): class RefreshPostponerTestCase(FHDLTestCase): def test_init(self): - m = Module() - m.submodules.dut = dut = RefreshPostponer(1) + dut = RefreshPostponer(1) def process(): self.assertFalse((yield dut.req_o)) - runSimulation(m, process, "test_refreshpostponer.vcd") + runSimulation(dut, process, "test_refreshpostponer.vcd") def test_delay(self): def generic_test(delay): - m = Module() - m.submodules.dut = dut = RefreshPostponer(delay) + dut = RefreshPostponer(delay) def process(): yield dut.req_i.eq(1) @@ -64,14 +61,13 @@ class RefreshPostponerTestCase(FHDLTestCase): self.assertTrue((yield dut.req_o)) - runSimulation(m, process, "test_refreshpostponer.vcd") + runSimulation(dut, process, "test_refreshpostponer.vcd") [generic_test(_) for _ in [1, 5, 10]] def test_req_not_stuck(self): def generic_test(delay): - m = Module() - m.submodules.dut = dut = RefreshPostponer(delay) + dut = RefreshPostponer(delay) def process(): yield dut.req_i.eq(1) @@ -86,7 +82,7 @@ class RefreshPostponerTestCase(FHDLTestCase): self.assertFalse((yield dut.req_o)) - runSimulation(m, process, "test_refreshpostponer.vcd") + runSimulation(dut, process, "test_refreshpostponer.vcd") [generic_test(_) for _ in [1, 5, 10]] @@ -110,12 +106,11 @@ class RefresherTestCase(FHDLTestCase): def test_init(self): def generic_test(postponing): - m = Module() - m.submodules.dut = dut = Refresher(self.settings, 100e6, postponing) + dut = Refresher(self.settings, 100e6, postponing) def process(): self.assertFalse((yield dut.cmd.valid)) - runSimulation(m, process, "test_refresher.vcd") + runSimulation(dut, process, "test_refresher.vcd") [generic_test(_) for _ in [1, 2, 4, 8]] diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index d05d934..2ceb47a 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -135,11 +135,9 @@ class SocTestCase(FHDLTestCase): yield def test_multiple_reads(self): - m = Module() soc = DDR3SoC(clk_freq=100e6, dramcore_addr=0x00000000, ddr_addr=0x10000000) - m.submodules += soc def process(): yield from SocTestCase.init_seq(soc.bus) @@ -153,14 +151,12 @@ class SocTestCase(FHDLTestCase): yield self.assertEqual(res, 0xACAB2020) - runSimulation(m, process, "test_soc_multiple_reads.vcd") + runSimulation(soc, process, "test_soc_multiple_reads.vcd") def test_interleaved_read_write(self): - m = Module() soc = DDR3SoC(clk_freq=100e6, dramcore_addr=0x00000000, ddr_addr=0x10000000) - m.submodules += soc def process(): yield from SocTestCase.init_seq(soc.bus) @@ -180,14 +176,12 @@ class SocTestCase(FHDLTestCase): res = yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128) self.assertEqual(res, 0xCAFE1000) - runSimulation(m, process, "test_soc_interleaved_read_write.vcd") + runSimulation(soc, process, "test_soc_interleaved_read_write.vcd") def test_sequential_reads(self): - m = Module() soc = DDR3SoC(clk_freq=100e6, dramcore_addr=0x00000000, ddr_addr=0x10000000) - m.submodules += soc def process(): yield from SocTestCase.init_seq(soc.bus) @@ -204,14 +198,12 @@ class SocTestCase(FHDLTestCase): yield from wb_read(soc.bus, 0x10000018 >> 2, 0xF, 128) yield from wb_read(soc.bus, 0x1000001C >> 2, 0xF, 128) - runSimulation(m, process, "test_soc_sequential_reads.vcd") + runSimulation(soc, process, "test_soc_sequential_reads.vcd") def test_random_memtest(self): - m = Module() soc = DDR3SoC(clk_freq=100e6, dramcore_addr=0x00000000, ddr_addr=0x10000000) - m.submodules += soc def process(): yield from SocTestCase.init_seq(soc.bus) @@ -230,14 +222,12 @@ class SocTestCase(FHDLTestCase): for i in range(n): self.assertEqual(memtest_values[i], (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256))) - runSimulation(m, process, "test_soc_random_memtest.vcd") + runSimulation(soc, process, "test_soc_random_memtest.vcd") def test_continuous_memtest(self): - m = Module() soc = DDR3SoC(clk_freq=100e6, dramcore_addr=0x00000000, ddr_addr=0x10000000) - m.submodules += soc def process(): yield from SocTestCase.init_seq(soc.bus) @@ -252,4 +242,4 @@ class SocTestCase(FHDLTestCase): for i in range(n): self.assertEqual(0xFACE0000 | i, (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256))) - runSimulation(m, process, "test_soc_continuous_memtest.vcd") + runSimulation(soc, process, "test_soc_continuous_memtest.vcd")