From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 23:04:33 +0000 (-0700)
Subject: Be more precise when connecting during ABC9 re-integration
X-Git-Tag: working-ls180~1237^2~139
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b3faf0246d46f31027ce2aade410e4325822b121;p=yosys.git

Be more precise when connecting during ABC9 re-integration
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 21d207d33..c3145dbe5 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -569,7 +569,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
 					if (!a_bit.wire) {
 						c->setPort("\\Y", module->addWire(NEW_ID));
-						module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1);
+						RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
+						log_assert(wire);
+						module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
 					}
 					else if (!lut_costs.empty() || !lut_file.empty()) {
 						RTLIL::Cell* driving_lut = nullptr;