From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Nov 2013 21:59:45 +0000 (+0100)
Subject: Fixed techmap of $gt and $ge with multi-bit outputs
X-Git-Tag: yosys-0.2.0~397
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b41740060b28039c7e01fede41e6affb91867e02;p=yosys.git

Fixed techmap of $gt and $ge with multi-bit outputs
---

diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index d89b39b8a..ca73f5bcd 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -855,9 +855,15 @@ output [Y_WIDTH-1:0] Y;
 ) ge_via_le (
 	.A(B),
 	.B(A),
-	.Y(Y)
+	.Y(Y[0])
 );
 
+generate
+	if (Y_WIDTH > 1) begin:V
+		assign Y[Y_WIDTH-1:1] = 0;
+	end
+endgenerate
+
 endmodule
 
 // --------------------------------------------------------
@@ -882,9 +888,15 @@ output [Y_WIDTH-1:0] Y;
 ) gt_via_lt (
 	.A(B),
 	.B(A),
-	.Y(Y)
+	.Y(Y[0])
 );
 
+generate
+	if (Y_WIDTH > 1) begin:V
+		assign Y[Y_WIDTH-1:1] = 0;
+	end
+endgenerate
+
 endmodule
 
 // --------------------------------------------------------