From: Eric Anholt <eric@anholt.net>
Date: Mon, 3 Dec 2018 23:28:49 +0000 (-0800)
Subject: v3d: Add support for flushing dirty TMU data at job end.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b417a9f7b26e46260044ce8adb16166aa0384396;p=mesa.git

v3d: Add support for flushing dirty TMU data at job end.

This will be needed for SSBOs and image_load_store.
---

diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 9258534a2e6..31395450153 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -174,6 +174,16 @@
     <value name="int" value="3" min_ver="42"/> <!-- clamp to integer RT's range -->
   </enum>
 
+  <enum name="L2T Flush Mode" prefix="L2T_FLUSH_MODE">
+    <!-- invalidates all cache lines -->
+    <value name="flush" value="0"/>
+    <!-- Invalidates dirty cachelines without writeback -->
+    <value name="clear" value="1"/>
+    <!-- Writes back dirty cachelines and marks them clean, without
+         invalidating -->
+    <value name="clean" value="2"/>
+  </enum>
+
   <enum name="Output Image Format" prefix="V3D_OUTPUT_IMAGE_FORMAT">
     <!--
 	Formats appear with their channels named from the low bits to
@@ -595,6 +605,19 @@
 
   <packet code="75" name="Flush Transform Feedback Data"/>
 
+  <packet code="76" name="L1 Cache Flush Control">
+    <field name="TMU Config Cache Clear" size="4" start="12" type="uint"/>
+    <field name="TMU Data Cache Clear" size="4" start="8" type="uint"/>
+    <field name="Uniforms Cache Clear" size="4" start="4" type="uint"/>
+    <field name="Instruction Cache Clear" size="4" start="0" type="uint"/>
+  </packet>
+
+  <packet code="77" name="L2T Cache Flush Control">
+    <field name="L2T Flush Mode" size="4" start="64" type="L2T Flush Mode"/>
+    <field name="L2T Flush End" size="32" start="32" type="address"/>
+    <field name="L2T Flush Start" size="32" start="0" type="address"/>
+  </packet>
+
   <struct name="Transform Feedback Output Data Spec" max_ver="33">
     <field name="First Shaded Vertex Value to output" size="8" start="0" type="uint"/>
     <field name="Number of consecutive Vertex Values to output as 32-bit values" size="4" start="8" type="uint" minus_one="true"/>
diff --git a/src/gallium/drivers/v3d/v3d_context.h b/src/gallium/drivers/v3d/v3d_context.h
index 9f52342d2dd..25be07c2437 100644
--- a/src/gallium/drivers/v3d/v3d_context.h
+++ b/src/gallium/drivers/v3d/v3d_context.h
@@ -308,6 +308,11 @@ struct v3d_job {
          */
         bool needs_flush;
 
+        /* Set if any shader has dirtied cachelines in the TMU that need to be
+         * flushed before job end.
+         */
+        bool tmu_dirty_rcl;
+
         /**
          * Set if a packet enabling TF has been emitted in the job (V3D 4.x).
          */
diff --git a/src/gallium/drivers/v3d/v3dx_rcl.c b/src/gallium/drivers/v3d/v3dx_rcl.c
index 17b30465c9d..45115c0b0cc 100644
--- a/src/gallium/drivers/v3d/v3dx_rcl.c
+++ b/src/gallium/drivers/v3d/v3dx_rcl.c
@@ -786,5 +786,20 @@ v3dX(emit_rcl)(struct v3d_job *job)
                 }
         }
 
+        if (job->tmu_dirty_rcl) {
+           cl_emit(&job->rcl, L1_CACHE_FLUSH_CONTROL, flush) {
+              flush.tmu_config_cache_clear = 0xf;
+              flush.tmu_data_cache_clear = 0xf;
+              flush.uniforms_cache_clear = 0xf;
+              flush.instruction_cache_clear = 0xf;
+           }
+
+           cl_emit(&job->rcl, L2T_CACHE_FLUSH_CONTROL, flush) {
+              flush.l2t_flush_mode = L2T_FLUSH_MODE_CLEAN;
+              flush.l2t_flush_start = cl_address(NULL, 0);
+              flush.l2t_flush_end = cl_address(NULL, ~0);
+           }
+        }
+
         cl_emit(&job->rcl, END_OF_RENDERING, end);
 }