From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 12 Sep 2015 08:39:39 +0000 (+0800)
Subject: build/xilinx: minor cleanup
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b43495aab16e7d09f184214b896aad28c094d337;p=litex.git

build/xilinx: minor cleanup
---

diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py
index 19896038..65126a10 100644
--- a/migen/build/xilinx/ise.py
+++ b/migen/build/xilinx/ise.py
@@ -4,7 +4,6 @@ import sys
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from migen.build.generic_platform import *
 from migen.build import tools
 from migen.build.xilinx import common
@@ -134,7 +133,7 @@ def _default_ise_path():
 
 
 def _default_source():
-    return False if sys.platform == "win32" else True
+    return sys.platform != "win32"
 
 
 class XilinxISEToolchain:
diff --git a/migen/build/xilinx/platform.py b/migen/build/xilinx/platform.py
index c5422282..d4ca4b18 100644
--- a/migen/build/xilinx/platform.py
+++ b/migen/build/xilinx/platform.py
@@ -17,7 +17,7 @@ class XilinxPlatform(GenericPlatform):
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict(common.xilinx_special_overrides)
         if self.device[:3] == "xc7":
-            so.update(dict(common.xilinx_s7_special_overrides))
+            so.update(common.xilinx_s7_special_overrides)
         so.update(special_overrides)
         return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)