From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jun 2020 03:53:52 +0000 (+0100)
Subject: refer to srr0/1 not a/b
X-Git-Tag: div_pipeline~567
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4393a92148c85223bf571d7f77ab2807a50ee2e;p=soc.git

refer to srr0/1 not a/b
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 67061cb4..964cd6b7 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -214,10 +214,10 @@ class TrapMainStage(PipeModBase):
                     ctrl_tmp.msr(MSR_DR) <= '1';
                 end if;
                 """
-                comb += nia_o.data.eq(br_ext(a_i[2:]))
+                comb += nia_o.data.eq(br_ext(srr0_i[2:]))
                 comb += nia_o.ok.eq(1)
                 comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
-                with m.If(a[MSR_PR]):
+                with m.If(srr1_i[MSR_PR]):
                         msr_o[MSR_EE].eq(1)
                         msr_o[MSR_IR].eq(1)
                         msr_o[MSR_DR].eq(1)