From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 11 Sep 2023 20:16:13 +0000 (-0700)
Subject: filter out addex when soc flag set
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b43bbb1870bfd5cd7fca3f95321b42321774c088;p=openpower-isa.git

filter out addex when soc flag set
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index c489cee7..90e3ac11 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -1,5 +1,6 @@
 import random
-from openpower.test.common import TestAccumulatorBase, skip_case
+from openpower.test.common import \
+    TestAccumulatorBase, skip_case, skip_case_if_flag
 from openpower.endian import bigendian
 from openpower.simulator.program import Program
 from openpower.decoder.selectable_int import SelectableInt
@@ -87,6 +88,7 @@ def check_addmeo_subfmeo_matches_reference(instr, case_filter, out):
 
 
 class ALUTestCase(TestAccumulatorBase):
+    @skip_case_if_flag('soc')
     def case_addex(self):
         lst = [f"addex 3, 4, 5, 0"]
         program = Program(lst, bigendian)
@@ -708,6 +710,8 @@ class ALUTestCase(TestAccumulatorBase):
             'addco.', 'subfco.', 'addeo.', 'subfeo.', 'addmeo.', 'subfmeo.',
             'addzeo.', 'subfzeo.', 'addex', 'nego.',
         }
+        if 'soc' in self.flags:
+            wanted_instrs.remove('addex')
         unary_inputs = {
             '0x0', '0x1', '0x2',
             '0xFFFFFFFFFFFFFFFF', '0xFFFFFFFFFFFFFFFE',