From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 06:00:38 +0000 (+0100)
Subject: add example code
X-Git-Tag: convert-csv-opcode-to-binary~5270
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4414b8173b818a55626319635d854b8b19d8cc8;p=libreriscv.git

add example code
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 164850ac5..564eca3c4 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -104,6 +104,7 @@
    \item Greatly-reduced I-cache load (and less reads)
    \item Amazingly, SIMD becomes (more) tolerable\\
 	     (corner-cases for setup and teardown are gone)
+   \item Modularity/Abstraction in both the h/w and the toolchain.
   \end{itemize}
   Note:
    \begin{itemize}