From: lkcl <lkcl@web>
Date: Fri, 1 Jan 2021 01:44:42 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~669
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b44bc33717fb62dc08eac746c6fcce308b11b72c;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index f7f34be17..62c7a961b 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -305,7 +305,7 @@ structure, where all types uint16_t etc. are in little-endian order:
 
 This means that Vector elements start from locations specified by 64 bit "register" but that from that location onwards the elements *overlap subsequent registers*.
 
-Here is another way to view the same concept:
+Here is another way to view the same concept, bearing in mind that it is assumed a LE memory order:
 
     uint8_t reg_sram[8*128];
     uint8_t *actual_bytes = &reg_sram[RA*8];