From: Marcin Kościelnicki <mwk@0x04.net>
Date: Sun, 2 Feb 2020 10:26:00 +0000 (+0100)
Subject: xilinx: use RAM32M/RAM64M for memories with two read ports
X-Git-Tag: working-ls180~827
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b44d0e041f09216dd90dccd3f18f146b1dfb7e92;p=yosys.git

xilinx: use RAM32M/RAM64M for memories with two read ports

This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
---

diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt
index 29f6b05cc..faf66bc18 100644
--- a/techlibs/xilinx/lutrams.txt
+++ b/techlibs/xilinx/lutrams.txt
@@ -153,7 +153,7 @@ endmatch
 
 match $__XILINX_RAM32X2Q
   min bits 5
-  min rports 3
+  min rports 2
   min wports 1
   make_outreg
   or_next_if_better
@@ -161,7 +161,7 @@ endmatch
 
 match $__XILINX_RAM64X1Q
   min bits 5
-  min rports 3
+  min rports 2
   min wports 1
   make_outreg
 endmatch