From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Feb 2020 14:38:13 +0000 (+0000)
Subject: zero out entirety of mask explicitly
X-Git-Tag: ls180-24jan2020~124
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b44df89c6c9179991d8e07ccbae73fb74a551b3c;p=ieee754fpu.git

zero out entirety of mask explicitly
---

diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index 7e5134fd..e5ae5576 100644
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -51,6 +51,7 @@ class ShifterMask(Elaboratable):
         # XXX ARGH, really annoying: simulation bug, can't use Cat(*bl).
         for j in range(bits.shape()[0]):
             comb += bits[j].eq(bl[j])
+        comb += self.mask.eq(C(0, self.mask.shape()))
         comb += self.mask.eq(Cat(minm, bits) & C(maxm, self.mask.shape()))
 
         return m