From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 29 Jul 2018 09:54:01 +0000 (+0100)
Subject: horrible clock-sync hack
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b454fb16bfe32de4af22c125247bb9ce1942a0df;p=pinmux.git

horrible clock-sync hack
---

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index e4df4b5..e7de196 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -245,6 +245,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
                     n_ = "{0}{1}".format(n, count)
                 else:
                     n_ = n
+                n_ = '{0}_{1}'.format(n_, pname)
                 ret.append(template.format("Bit#(1)", n_, ck, spc))
             if typ == 'in' or typ == 'inout':
                 #fname = self.pinname_in(pname)