From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 17 Jul 2020 12:13:51 +0000 (+0100)
Subject: whitespace
X-Git-Tag: semi_working_ecp5~707
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4562c8aa2a29589f28a5ecf63611aa1a9515d54;p=soc.git

whitespace
---

diff --git a/libreriscv b/libreriscv
index d83e5ccb..12e9237b 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit d83e5ccbacd56e762bedc660cdd930264e12b81b
+Subproject commit 12e9237b896ad233cb18946b34dab17d976f415c
diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index 970ac7cf..b029f04b 100644
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -54,7 +54,8 @@ class DivPipeKindConfig:
 class DivPipeKind(enum.Enum):
     # use ieee754.div_rem_sqrt_rsqrt.core.DivPipeCore*
     DivPipeCore = enum.auto()
-    # use nmigen's built-in div and rem operators -- only suitable for simulation
+    # use nmigen's built-in div and rem operators -- only suitable for
+    # simulation
     SimOnly = enum.auto()
     # use a FSM-based div core
     FSMCore = enum.auto()
@@ -142,14 +143,17 @@ class CoreBaseData(DivInputData):
 
 class CoreInputData(CoreBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec, pspec.div_pipe_kind.config.core_input_data_class)
+        super().__init__(pspec,
+                         pspec.div_pipe_kind.config.core_input_data_class)
 
 
 class CoreInterstageData(CoreBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec, pspec.div_pipe_kind.config.core_interstage_data_class)
+        super().__init__(pspec,
+                         pspec.div_pipe_kind.config.core_interstage_data_class)
 
 
 class CoreOutputData(CoreBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec, pspec.div_pipe_kind.config.core_output_data_class)
+        super().__init__(pspec,
+                         pspec.div_pipe_kind.config.core_output_data_class)